Patents by Inventor William G. Vandenberghe

William G. Vandenberghe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9741416
    Abstract: Memory devices based on gate controlled ferromagnetism and spin-polarized current injection are provided. The device structure can include a two dimensional (2D) topological insulator (TI) having an active area body. One or a pair of ferromagnetic storage units are provided on top of the 2D TI with a dielectric and a gate thereon. A first contact can be at one end of the 2D TI and a second contact can be at the other end of the 2D TI, with the one or pair of ferromagnetic storage units on the 2D TI between the two contacts to facilitate 2D TI transport along a one-dimensional edge of the first and/or second lateral side. Application of biases via the gate and the first and second contacts enable read and write operations.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: August 22, 2017
    Assignee: Board of Regents, the University of Texas System
    Inventors: William G. Vandenberghe, Christopher L. Hinkle, Massimo V. Fischetti
  • Patent number: 8404545
    Abstract: A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced).
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: March 26, 2013
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: William G. Vandenberghe, Anne S. Verhulst
  • Patent number: 8148220
    Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents an elongate monocrystalline nanostructure-based TFET with a heterostructure made of a different semiconducting material (e.g. germanium (Ge)) is used. An elongate monocrystalline nanostructure made of a different semiconducting material is introduced which acts as source (or alternatively drain) region of the TFET. The introduction of the heterosection is such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: April 3, 2012
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Anne S. Verhulst, William G. Vandenberghe
  • Publication number: 20120045879
    Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents an elongate monocrystalline nanostructure-based TFET with a heterostructure made of a different semiconducting material (e.g. germanium (Ge)) is used. An elongate monocrystalline nanostructure made of a different semiconducting material is introduced which acts as source (or alternatively drain) region of the TFET. The introduction of the heterosection is such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations.
    Type: Application
    Filed: November 1, 2011
    Publication date: February 23, 2012
    Applicants: Katholieke Universiteit Leuven, K.U. LEUVEN R&D, IMEC
    Inventors: Anne S. Verhulst, William G. Vandenberghe
  • Patent number: 8120115
    Abstract: A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced).
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: February 21, 2012
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: William G. Vandenberghe, Anne S. Verhulst
  • Patent number: 8072012
    Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents an elongate monocrystalline nanostructure-based TFET with a heterostructure made of a different semiconducting material (e.g. germanium (Ge)) is used. An elongate monocrystalline nanostructure made of a different semiconducting material is introduced which acts as source (or alternatively drain) region of the TFET. The introduction of the heterosection is such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: December 6, 2011
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Anne S. Verhulst, William G. Vandenberghe
  • Publication number: 20080067607
    Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents an elongate monocrystalline nanostructure-based TFET with a heterostructure made of a different semiconducting material (e.g. germanium (Ge)) is used. An elongate monocrystalline nanostructure made of a different semiconducting material is introduced which acts as source (or alternatively drain) region of the TFET. The introduction of the heterosection is such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 20, 2008
    Applicants: Interuniversitair Microelektronica Centrum (IMEC), Katholieke Universiteit Leuven K.U.LEUVEN R&D
    Inventors: Anne S. Verhulst, William G. Vandenberghe