Abstract: A local area network (LAN) backbone is implemented within an environment such as a self-contained environment (e.g., an automobile, an aircraft, a train, a ship, and/or any other environment). The LAN backbone is affected by AWGN, NBI, and/or impulse noise (noise). The LAN backbone supports communications based on an Ethernet communication protocol (e.g., a 1000Base-T1 based system that includes at least one single twisted pair). A device receives a first LDPC coded signal via the LAN backbone and decodes it to recover an input signal of a control system. The device also uses soft information generated during the decoding to compensate for the noise affecting the LAN backbone and then processes the input signal to generate a control signal for the control system. The device then and encodes the control signal to generate a second LDPC coded signal and transmits the second LDPC coded signal via the LAN backbone.

Abstract: A local area network (LAN) backbone is implemented within an environment such as a self-contained environment (e.g., an automobile, an aircraft, a train, a ship, and/or any other environment). The LAN backbone is affected by AWGN, NBI, and/or impulse noise (noise). The LAN backbone supports communications based on an Ethernet communication protocol (e.g., a 1000Base-T1 based system that includes at least one single twisted pair). A device receives a first LDPC coded signal via the LAN backbone and decodes it to recover an input signal of a control system. The device also uses soft information generated during the decoding to compensate for the noise affecting the LAN backbone and then processes the input signal to generate a control signal for the control system. The device then and encodes the control signal to generate a second LDPC coded signal and transmits the second LDPC coded signal via the LAN backbone.

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: A servo writer includes a servo data generation module that generates servo data corresponding to a plurality of servo wedges and a plurality of tracks of a disk, the servo data including track identification data that is repetition coded. A servo write module writes the servo data on the disk.

Abstract: Sliding block traceback decoding of block codes. Block by block basis decoding is performed in which a single block, and its corresponding overlap portion, are processed during a given time. The traceback saves a record of decision (e.g., among possible trellis branches between various trellis stages) and constructs only the surviving paths through each individual block. Since only one block (by also employing its corresponding overlap portion) is decoded per time, the traceback through the coded block signal is short. One block of the coded block signal is decoded at a time, and certain resulting information (e.g., bit estimates and/or states) of a first decoded block can be leveraged when decoding a second/adjacent block.

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: A write channel includes a pre-encoding module that encodes write data to produce pre-encoded data. An error correcting code (ECC) module generates ECC data based on the pre-encoded data. A post-encoding module encodes the ECC data to produce post-encoded data. A combining module combines the pre-encoded data and the post-encoded data for writing to the storage medium.

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: Timing recovery optimization using disk clock. A novel means is presented to perform and provide control of the sampling frequency of a signal that is read from a disk within a hard disk drive (HDD). Two separate, yet somewhat cooperating control loops are employed to provide feedback control of the sampling frequency of the signal that is read from disk. A timing recovery loop and a disk clock loop operate in conjunction with one another according to some desired manner (which can be predetermined or adaptive) to ensure that the sampling of the signal is performed to a very accurate degree. In one implementation, the timing recovery loop governs the sampling rate until the disk clock loop has locked, from which time either the disk clock loop govern the sampling or some combination of the signals provided from the two loops govern the sampling.

Abstract: Reading data from a magnetic storage media with an analog front end (AFE) coupled to an all digital read channel compensation architecture. A read head passes over magnetic storage media to produce an analog signal. The analog signal is amplified such that the range of the amplified analog signal substantial matches a range of the analog to digital converter (ADC) used to sample the analog signal. A baseline adjust is performed on the amplified analog signal to center the amplified analog signal to a midscale of the ADC. The amplified analog signal may be sampled where the sampling is data frequency locked by a data lock clock (DLC) tracking module. A digital signal may then be produced from the amplified analog signal where this signal is read channel compensated in the digital domain to produce a digital signal which is then processed with a sequence detector.

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) correction module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract: Joint decoding of ISI (Inter-Symbol Interference) channel and modulation codes. A single, combined ISI and modulation decoding module is operable to process a signal received from an ISI communication channel and directly to generate a soft estimate of information encoded therein. A single module employs a decoding transfer function that is substantially matched to the communication channel that introduces the ISI and the modulation encoding performed on the information before being launched into the ISI communication channel. Such operations and functionality are adaptable to a variety of modulation coding systems that are tailored to deal with communication systems that introduce ISI. Moreover, such operations and functionality are extendable to communication systems employing an error correction code (ECC) such as Reed-Solomon (RS) coding as well as ECCs of an iterative nature such as LDPC (Low Density Parity Check) coding, turbo coding, and/or turbo trellis code modulation (TTCM) coding.

Abstract: A read channel in that reads data from a magnetic storage media. An analog signal produced by passing a read head over magnetic storage media is amplified to match the range of an analog to digital converter (ADC) range. A baseline adjustment is performed on the amplified analog signal to center the amplified analog signal to a midscale of the ADC, which may be based on an error feedback signal and/or a decision feedback signal. Read channel compensation may then be performed after the baseline adjustment has been applied. The read channel compensated analog signal is sampled with the ADC to produce a digital signal. This digital signal may be filtered and a bit sequence may then be detected from the filtered digital signal. The EFB signal and/or the DFB signal may be produced in the digital domain based on the digital signal and the detected bit sequences.

Abstract: A disk drive controller includes a servo system operable to associate a time stamp with an arrival of a servo wedge, a firmware loop and core PLLs in the read channel. The firmware loop is operable to determine a period between the arrival of a pair of consecutive servo wedges and produce a desired frequency of when to read/write data to disk based on the period between the arrival of a pair of consecutive servo wedges. Processing circuitry is operable to adjust a clock signal, wherein the clock signal itself is not locked to the data and produce a fine control signal for the core PLLs in the read channel. These core PLLs are operable to determine a phase and/or frequency associated with when an analog signal is sampled and/or written to disk, wherein these core PLLs comprises Fractional N Sigma Delta PLLs.

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) correction module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract: A servo writer includes a servo data generation module that generates servo data corresponding to a plurality of servo wedges and a plurality of tracks of a disk, the servo data including track identification data that is repetition coded. A servo write module writes the servo data on the disk.

Abstract: A servo writer includes a servo data generation module that generates servo data corresponding to a plurality of servo wedges and a plurality of tracks of a disk, the servo data including burst data that is repetition coded. A servo write module writes the servo data on the disk.

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) collection module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract: A servo writer includes a servo data generation module that generates servo data corresponding to a plurality of servo wedges and a plurality of tracks of a disk, the servo data including track identification data that is repetition coded. A servo write module writes the servo data on the disk.

Abstract: Reading data from a magnetic storage media with an analog front end (AFE) coupled to an all digital read channel compensation architecture. A read head passes over magnetic storage media to produce an analog signal. The analog signal is amplified such that the range of the amplified analog signal substantial matches a range of the analog to digital converter (ADC) used to sample the analog signal. A baseline adjust is performed on the amplified analog signal to center the amplified analog signal to a midscale of the ADC. The amplified analog signal may be sampled where the sampling is data frequency locked by a data lock clock (DLC) tracking module. A digital signal may then be produced from the amplified analog signal where this signal is read channel compensated in the digital domain to produce a digital signal which is then processed with a sequence detector.