Abstract: A data-processing-circuit comprising: a clock-input-terminal configured to receive a clock-signal; a data-output-terminal configured to provide a data-output-signal; an adjustable-driver-buffer configured to: receive a data-signal; and apply a driver-strength-value to the data-signal in order to provide a data-output-signal, wherein the current level of the data-output-signal is based on the driver-strength-value; and a driver-control-module comprising: a time-alignment-module configured to: process the clock-signal and the data-output-signal in order to determine a timing-delay-signal that is representative of a time delay between: a transition in the clock-signal; and a transition in the data-output-signal; provide the driver-strength-value for the adjustable-driver-buffer based on the timing-delay-signal and a target-delay-signal, wherein the driver-strength-value is for reducing a difference between: the timing-delay-signal; and the target-delay-signal.

Abstract: A data-processing-circuit comprising: a clock-input-terminal configured to receive a clock-signal; a data-output-terminal configured to provide a data-output-signal; an adjustable-driver-buffer configured to: receive a data-signal; and apply a driver-strength-value to the data-signal in order to provide a data-output-signal, wherein the current level of the data-output-signal is based on the driver-strength-value; and a driver-control-module comprising: a time-alignment-module configured to: process the clock-signal and the data-output-signal in order to determine a timing-delay-signal that is representative of a time delay between: a transition in the clock-signal; and a transition in the data-output-signal; provide the driver-strength-value for the adjustable-driver-buffer based on the timing-delay-signal and a target-delay-signal, wherein the driver-strength-value is for reducing a difference between: the timing-delay-signal; and the target-delay-signal.