Abstract: A computer implemented method for determining whether a first (S/R-Latch) description of a state element that is implemented as a set of interconnected electrical devices can be replaced by a second (D-Latch) description of the state element. The method includes the steps of providing a representation of the S/R-Latch description to the computer, causing the computer to apply to the representation a set of rules that define a relationship between the S/R-Latch description and the D-Latch description and that are independent of a topology of the set of interconnected devices, and causing the computer to replace the S/R-Latch description with the D-Latch description of the state element if the representation satisfies the rules.

Abstract: A method for static analysis of a software model of a circuit clocked by two clocks where the two clocks' periods are multiples of a greatest common divisor period. In the invention, a composite clock is determined with a period equal to the least common multiple of the periods of the two clocks, and the model is statically analyzed relative to the composite clock.