Patents by Inventor William H. Speece
William H. Speece has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7052973Abstract: A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.Type: GrantFiled: March 29, 2004Date of Patent: May 30, 2006Assignee: Intersil Americas Inc.Inventors: Jack H. Linn, William H. Speece, Michael G. Shlepr, George V. Rouse
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Patent number: 6825532Abstract: A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.Type: GrantFiled: May 1, 2001Date of Patent: November 30, 2004Assignee: Intersil Americas Inc.Inventors: Jack H. Linn, William H. Speece, Michael G. Shlepr, George V. Rouse
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Publication number: 20040180512Abstract: A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.Type: ApplicationFiled: March 29, 2004Publication date: September 16, 2004Applicant: Intersil Americas Inc.Inventors: Jack H. Linn, William H. Speece, Michael G. Shlepr, George V. Rouse
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Publication number: 20010016399Abstract: In a method for forming a bonded semiconductor-on-insulator substrate for the fabrication of semiconductor devices and integrated circuits, a surface of a wafer of a monocrystalline semiconductor material is implanted with ions of the semiconductor material a to a selected depth in the wafer to form, adjacent to the surface, an amorphous layer of the semiconductor material. The layer of amorphous semiconductor material extends to a substantially planar zone disposed at substantially the selected depth and comprising the monocrystalline semiconductor material damaged by lattice defects, i.e., end-of-range implant damage. Undamaged material below the selected depth comprises a first layer of the monocrystalline semiconductor material.Type: ApplicationFiled: May 1, 2001Publication date: August 23, 2001Applicant: HARRIS CORPORATIONInventors: Jack H. Linn, William H. Speece, Michael G. Shlepr, George V. Rouse
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Patent number: 6255195Abstract: In a method for forming a bonded semiconductor-on-insulator substrate for the fabrication of semiconductor devices and integrated circuits, a surface of a wafer of a monocrystalline semiconductor material is implanted with ions of the semiconductor material a to a selected depth in the wafer to form, adjacent to the surface, an amorphous layer of the semiconductor material. The layer of amorphous semiconductor material extends to a substantially planar zone disposed at substantially the selected depth and comprising the monocrystalline semiconductor material damaged by lattice defects, i.e., end-of-range implant damage. Undamaged material below the selected depth comprises a first layer of the monocrystalline semiconductor material.Type: GrantFiled: February 22, 1999Date of Patent: July 3, 2001Assignee: Intersil CorporationInventors: Jack H. Linn, William H. Speece, Michael G. Shlepr, George V. Rouse
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Patent number: 5517047Abstract: Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.Type: GrantFiled: August 9, 1994Date of Patent: May 14, 1996Assignee: Harris CorporationInventors: Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller, William H. Speece
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Patent number: 5391903Abstract: A silicon layer formed atop a sapphire substrate is selectively recrystallized such that the original degraded quality of the crystallinity of an N-well region where a P-channel device is to be formed is enhanced, so that leakage in the P-channel device is reduced, while the high ultraviolet reflectance number of a P-well region where an N-channel device resides remains unaffected. The process according to the present invention involves implanting silicon into only that portion of the silicon layer where an N-conductivity well region for a P-channel device is to be formed. An N-conductivity type impurity is introduced into the silicon-implanted portion of the silicon layer, to form the N-conductivity well region. The structure is then annealed at a relatively low temperature for several minutes, which is sufficient to activate the phosphorus and to cause local recrystallization of the N-well region of the silicon layer, without essentially causing a redistribution of the phosphorus.Type: GrantFiled: December 21, 1993Date of Patent: February 21, 1995Assignee: Harris CorporationInventors: Kurt Strater, Edward F. Hand, William H. Speece
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Patent number: 5362667Abstract: Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.Type: GrantFiled: July 28, 1992Date of Patent: November 8, 1994Assignee: Harris CorporationInventors: Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller, William H. Speece
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Patent number: 5298434Abstract: A preamorphized silicon layer formed atop a sapphire substrate is selectively recrystallized such that the original degraded quality of the crystallinity of an N-well region where a P-channel device is to be formed is enhanced, so that leakage in the P-channel device is reduced, while the high UVR number of a P-well region where an N-channel device resides remains unaffected. The process according to the present invention involves implanting a recrystallization-inducing element, such as silicon, into only that portion of the preamorphized silicon layer where an N-conductivity well region for a P-channel device is to be formed. An N-conductivity type impurity is introduced into the silicon-implanted portion of the preamorphized silicon layer, to form the N-conductivity well region.Type: GrantFiled: February 7, 1992Date of Patent: March 29, 1994Assignee: Harris CorporationInventors: Kurt Strater, Edward F. Hand, William H. Speece
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Patent number: 5293052Abstract: An SOI/SOS thin film MOS mesa architecture has its body/channel region extended beyond the source and drain regions and the impurity concentration is increased at an end portion of the extended body region, so as to provide a channel stop region that is effective to functionally interrupt a current leakage path or `parasitic` N-channel that may be induced along sidewall surface of the P-type material of the body/channel region. In addition, in order to inhibit radiation-induced leakage along a backside interface of the extended body region abutting an underlying dielectric substrate, a portion of the extended body region between the channel stop region and the body/channel region has an impurity concentration profile that is increased at the interface of the extended body region with the underlying dielectric substrate.Type: GrantFiled: March 23, 1992Date of Patent: March 8, 1994Assignee: Harris CorporationInventors: Richard D. Cherne, James F. Buller, William H. Speece
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Patent number: H1435Abstract: An SOI/SOS thin film MOS mesa architecture has its body/channel region extended beyond the source and drain regions and the impurity concentration is increased at a selected portion (e.g. an end portion) of the extended body region, so as to provide both a body tie access location which enables the body/channel region to be terminated to a prescribed bias voltage (e.g. Vss), and a channel stop region that is effective to functionally interrupt a current leakage path or `parasitic` N-channel that may be induced along sidewall surface of the P-type material of the body/channel region. In another embodiment, ionizing radiation-induced inversion of the sidewalls of the P-type body/channel region is prevented by an asymmetric sidewall channel stop structure formed in opposite end portions of the source region.Type: GrantFiled: October 21, 1991Date of Patent: May 2, 1995Inventors: Richard D. Cherne, Jack E. Clark, II, Glenn A. Dejong, Richard L. Lichtel, Wesley H. Morris, William H. Speece