Patents by Inventor William J. Butera
William J. Butera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11656662Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.Type: GrantFiled: February 11, 2021Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Simon C. Steely, Jr., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
-
Patent number: 11269805Abstract: Embodiments herein may present a multi-tile processor including a plurality of processor tiles, and a plurality of interconnects selectively coupling the plurality of processor tiles to each other. A first processor tile may include a memory to store a bulletin board to hold a message, an execution unit, and an encapsulated software module. The encapsulated software module may select a second processor tile coupled with the first processor tile by an interconnect to be a part of a signal pathway. The second processor tile may be selected based on a selection criterion of the signal pathway and the message held in the bulletin board. The encapsulated software module may post and read a message at the bulletin board stored in the memory, or read a message from a bulletin board stored in a memory of the second processor tile. Other embodiments may be described and/or claimed.Type: GrantFiled: May 15, 2018Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: William J. Butera, Simon C. Steely, Jr., Richard J. Dischler
-
Publication number: 20210255674Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: February 11, 2021Publication date: August 19, 2021Inventors: Simon C. Steely, JR., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
-
Patent number: 10963022Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.Type: GrantFiled: April 29, 2020Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: Simon C. Steely, Jr., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
-
Patent number: 10891254Abstract: Embodiments relate to a computational device including multiple processor tiles on a die that may have multiple switchable topologies. A topology of the computational device may include one or more virtual circuits. A virtual circuit may include multiple processor tiles. A processor tile of a virtual circuit of a topology may include a configuration vector to control a connection between the processor tile and a neighboring processor tile. A first topology of the computation device may correspond to a first phase of a computation of a program, and a second topology of the computation device may correspond to a second phase of the computation of the program. Other embodiments may be described and/or claimed.Type: GrantFiled: June 29, 2017Date of Patent: January 12, 2021Assignee: Intel CorporationInventors: William J. Butera, Simon C. Steely, Jr., Richard J. Dischler
-
Publication number: 20200371566Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 29, 2020Publication date: November 26, 2020Inventors: Simon C. Steely, JR., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
-
Patent number: 10691182Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.Type: GrantFiled: May 20, 2019Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Simon C. Steely, Jr., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
-
Publication number: 20190354146Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: May 20, 2019Publication date: November 21, 2019Inventors: Simon C. Steely, JR., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
-
Publication number: 20190042534Abstract: Embodiments herein may present a multi-tile processor including a plurality of processor tiles, and a plurality of interconnects selectively coupling the plurality of processor tiles to each other. A first processor tile may include a memory to store a bulletin board to hold a message, an execution unit, and an encapsulated software module. The encapsulated software module may select a second processor tile coupled with the first processor tile by an interconnect to be a part of a signal pathway. The second processor tile may be selected based on a selection criterion of the signal pathway and the message held in the bulletin board. The encapsulated software module may post and read a message at the bulletin board stored in the memory, or read a message from a bulletin board stored in a memory of the second processor tile. Other embodiments may be described and/or claimed.Type: ApplicationFiled: May 15, 2018Publication date: February 7, 2019Inventors: William J. Butera, Simon C. Steely, JR., Richard J. Dischler
-
Publication number: 20180113838Abstract: Embodiments relate to a computational device including multiple processor tiles on a die that may have multiple switchable topologies. A topology of the computational device may include one or more virtual circuits. A virtual circuit may include multiple processor tiles. A processor tile of a virtual circuit of a topology may include a configuration vector to control a connection between the processor tile and a neighboring processor tile. A first topology of the computation device may correspond to a first phase of a computation of a program, and a second topology of the computation device may correspond to a second phase of the computation of the program. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 29, 2017Publication date: April 26, 2018Inventors: William J. Butera, Simon C. Steely, JR., Richard J. Dischler
-
Publication number: 20110238189Abstract: A method and apparatus controls a plant using feedback signals. A procedural description of a feedback control process for the plant is translated into a set of objects, wherein each object is a portion of the procedural description, wherein each object is a strictly-encapsulated and autonomous software module, wherein the objects execute in a platform, and wherein the platform includes a set of nodes embedded in the plant and each node includes a processor. A feedback signals is generated by passing messages between the set of the objects in response to an operation of the plant.Type: ApplicationFiled: March 26, 2010Publication date: September 29, 2011Inventors: William J. Butera, William S. Yerazunis
-
Patent number: 5003377Abstract: Methods and systems for adding additional information to broadcast motion picture signals so that an advanced receiver can decode that information to provide improved picture quality, while a standard receiver will display an image with minimally visible impairments. In particular, chrominance information can be generated at a fraction of the frame rate and the alternate frames then used to encode additional data, such as high definition luminance information in the chrominance signal.Type: GrantFiled: January 12, 1989Date of Patent: March 26, 1991Assignee: Massachusetts Institute of TechnologyInventors: Andrew B. Lippman, Edward H. Adelson, William J. Butera
-
Patent number: 4987480Abstract: Image encoding apparatus and methods include recursively decomposing the luminance values of sequential frames into spatio-temporal spectral components, by quadrature mirror filter (QMF) processing of the luminance values. The filtered signals are subsampled, and each decomposed level of the spectral components is coded by vector quantization.Type: GrantFiled: July 11, 1989Date of Patent: January 22, 1991Assignee: Massachusetts Institute of TechnologyInventors: Andrew B. Lippman, William J. Butera
-
Patent number: 4530612Abstract: Rather than repeatedly using the entire length of a multi-color print ribbon in an impact printer until the reaching of a lower quality threshold requires replacement of the ribbon, this invention causes only a subsection of limited length of the ribbon to be used until the lower quality threshold of any one of the color tracks of this subsection is reached, after which the ribbon is advanced to enable use of a fresh subsection.The quality status of the currently used subsection may be monitored by counting the number of impacts on each individual color track and comparing that number with a predetermined, stored value, or by shining light through the ribbon and optically comparing the passing light with a preset value. The method is flexible enough to permit manual advance of the ribbon to a fresh subsection in case a printing job requires highest possible quality.Type: GrantFiled: August 5, 1983Date of Patent: July 23, 1985Assignee: International Business Machines Corp.Inventors: William J. Butera, Peter Stucki