Patents by Inventor William J. Clarke
William J. Clarke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9355746Abstract: Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.Type: GrantFiled: September 30, 2014Date of Patent: May 31, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luiz C. Alves, William J. Clarke, Christopher R. Conklin, William V. Huott, Kevin W. Kark, Thomas J. Knips, K. Paul Muller
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Patent number: 9166587Abstract: A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.Type: GrantFiled: March 13, 2013Date of Patent: October 20, 2015Assignee: International Business Machines CorporationInventors: Luiz C. Alves, William J. Clarke, K. Paul Muller, Robert B. Tremaine
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Publication number: 20150262713Abstract: Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.Type: ApplicationFiled: September 30, 2014Publication date: September 17, 2015Inventors: Luiz C. Alves, William J. Clarke, Christopher R. Conklin, William V. Huott, Kevin W. Kark, Thomas J. Knips, K. Paul Muller
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Publication number: 20150262711Abstract: Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.Type: ApplicationFiled: March 12, 2014Publication date: September 17, 2015Applicant: International Business Machines CorporationInventors: Luiz C. Alves, William J. Clarke, Christopher R. Conklin, William V. Huott, Kevin W. Kark, Thomas J. Knips, K. Paul Muller
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Patent number: 9136019Abstract: Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.Type: GrantFiled: March 12, 2014Date of Patent: September 15, 2015Assignee: International Business Machines CorporationInventors: Luiz C. Alves, William J. Clarke, Christopher R. Conklin, William V. Huott, Kevin W. Kark, Thomas J. Knips, K. Paul Muller
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Patent number: 8856620Abstract: Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.Type: GrantFiled: December 11, 2013Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Patrick J. Meaney, William J. Clarke, Eldee Stephens, Judy S. Johnson
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Patent number: 8843806Abstract: Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.Type: GrantFiled: January 19, 2012Date of Patent: September 23, 2014Assignee: International Business Machines CorporationInventors: Patrick J. Meaney, William J. Clarke, Eldee Stephens, Judy S. Johnson
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Publication number: 20140101518Abstract: Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: International Business Machines CorporationInventors: Patrick J. Meaney, William J. Clarke, Eldee Stephens, Judy S. Johnson
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Publication number: 20130265080Abstract: A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.Type: ApplicationFiled: March 13, 2013Publication date: October 10, 2013Inventors: Luiz C. Alves, William J. Clarke, K. Paul Muller, Robert B. Tremaine
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Patent number: 8513972Abstract: A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.Type: GrantFiled: January 18, 2012Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Luiz C. Alves, William J. Clarke, K. Paul Muller, Robert B. Tremaine
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Publication number: 20130191703Abstract: Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.Type: ApplicationFiled: January 19, 2012Publication date: July 25, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Patrick J. Meaney, William J. Clarke, Eldee Stephens, Judy S. Johnson
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Publication number: 20130181738Abstract: A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.Type: ApplicationFiled: January 18, 2012Publication date: July 18, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luiz C. Alves, William J. Clarke, K. Paul Muller, Robert B. Tremaine
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Patent number: 8041989Abstract: A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.Type: GrantFiled: June 28, 2007Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Luis A. Lastras-Montano, James A. O'Connor, Luiz C. Alves, William J. Clarke, Timothy J. Dell, Thomas J. Dewkett, Kevin C. Gower
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Patent number: 8041990Abstract: A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.Type: GrantFiled: June 28, 2007Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: James A. O'Connor, Luis A. Lastras-Montano, Luis C. Alves, William J. Clarke, Timothy J. Dell, Thomas J. Dewkett, Kevin C. Gower
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Publication number: 20090006886Abstract: A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.Type: ApplicationFiled: June 28, 2007Publication date: January 1, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James A. O'Connor, Luis A. Lastras-Montano, Luis C. Alves, William J. Clarke, Timothy J. Dell, Thomas J. Dewkett, Kevin C. Gower
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Publication number: 20090006900Abstract: A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.Type: ApplicationFiled: June 28, 2007Publication date: January 1, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luis A. Lastras-Montano, James A. O'Connor, Luiz C. Alves, William J. Clarke, Timothy J. Dell, Thomas J. Dewkett, Kevin C. Gower
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Patent number: 5106423Abstract: A method of grouting porous gas--and petroleum--bearing formations with a cementitious material comprising ultrafine ground slag is useful for primary and remedial cementing of a wellbore. A composition is provided which comprises water, a dispersant, slag and an accelerator to activate the slag.Type: GrantFiled: June 24, 1991Date of Patent: April 21, 1992Assignee: Geochemical CorporationInventor: William J. Clarke
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Patent number: 5026215Abstract: A method of grouting formations with a cementitious material comprising microfine ground slag is useful for stabilizing and strenghtening soil and rock formations as well as underground structures associated with buildings, tunnels and dams. A composition is provided which comprises water, a dispersant, slag and an accelerator to activate the slag. The method and composition are particularly useful for preventing permeation of water such as for grouting dam curtains and containing and stabilizing hazardous wastes including nuclear waste material.Type: GrantFiled: December 2, 1988Date of Patent: June 25, 1991Assignee: Geochemical CorporationInventor: William J. Clarke
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Patent number: 4897119Abstract: Disclosed is a novel composition comprising water, ground blast furnace slag and a low molecular weight polymeric dispersant. The dispersant is a polymer of acrylic acid, having a molecular weight between 1000 and 20,000, and being in the form of the acid or the salt of an alkali metal or ammonia. A process for preparing a dispersion having the novel composition is also disclosed.Type: GrantFiled: January 11, 1988Date of Patent: January 30, 1990Assignees: Geochemical Corporation, W. J. ClarkeInventor: William J. Clarke
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Patent number: 4761183Abstract: A grouting composition, a method of grouting and a formation so grouted are disclosed. The composition comprises a very small particle size slag, an equal or greater weight of water and the optional components cement, alkali silicate, anionic dispersant, a source of orthophosphate ions, sodium hydroxide and sodium carbonate. The grout is particularly adapted to the treatment of "tight" or low permeability formations being low in viscosity and having controllable set time and hardening time as well as high strength upon hardening. Being based on slag, a byproduct, the grout is economical.Type: GrantFiled: January 20, 1987Date of Patent: August 2, 1988Assignees: Geochemical Corporation, William J. ClarkeInventor: William J. Clarke