Patents by Inventor William J. Lambert
William J. Lambert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240164010Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.Type: ApplicationFiled: January 22, 2024Publication date: May 16, 2024Applicant: Intel CorporationInventors: Sidharth Dalmia, Zhenguo Jiang, William J. Lambert, Kirthika Nahalingam, Swathi Vijayakumar
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Patent number: 11937367Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.Type: GrantFiled: July 3, 2023Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Sidharth Dalmia, Zhenguo Jiang, William J. Lambert, Kirthika Nahalingam, Swathi Vijayakumar
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Publication number: 20240072419Abstract: Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Applicant: Intel CorporationInventors: Sidharth Dalmia, Jonathan Jensen, Ozgur Inac, Trang Thai, William J. Lambert, Benjamin Jann
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Patent number: 11912545Abstract: A wireless hoist system including a first hoist device having a first motor and a first wireless transceiver and a second hoist device having a second motor and a second wireless transceiver. The wireless hoist system includes a controller in wireless communication with the first wireless transceiver and the second wireless. The controller is configured to receive a user input and determine a first operation parameter and a second operation parameter based on the user input. The controller is also configured to provide, wirelessly, a first control signal indicative of the first operation parameter to the first hoist device and provide, wirelessly, a second control signal indicative of the second operation parameter to the second hoist device. The first hoist device operates based on the first control signal and the second hoist device operates based on the second control signal.Type: GrantFiled: June 26, 2020Date of Patent: February 27, 2024Assignee: Milwaukee Electric Tool CorporationInventors: Matthew Post, Gareth Mueckl, Matthew N. Thurin, Joshua D. Widder, Timothy J. Bartlett, Patrick D. Gallagher, Jarrod P. Kotes, Karly M. Schober, Kenneth W. Wolf, Terry L. Timmons, Mallory L. Marksteiner, Jonathan L. Lambert, Ryan A. Spiering, Jeremy R. Ebner, Benjamin A. Smith, James Wekwert, Brandon L. Yahr, Troy C. Thorson, Connor P. Sprague, John E. Koller, Evan M. Glanzer, John S. Scott, William F. Chapman, III, Timothy R. Obermann
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Publication number: 20240063120Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, Shawna M. Liff, Debendra Mallik, Christopher M. Pelto, Kimin Jun, Johanna M. Swan, Lei Jiang, Feras Eid, Krishna Vasanth Valavala, Henning Braunisch, Patrick Morrow, William J. Lambert
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Publication number: 20240063202Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies in a dielectric material, adjacent layers in the plurality of layers being coupled together by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; a package substrate coupled to a first side of the plurality of layers by second interconnects; a support structure coupled to a second side of the plurality of layers by third interconnects, the second side being opposite to the first side; and capacitors in at least the plurality of layers or the support structure. The capacitors are selected from at least planar capacitors, deep trench capacitors and via capacitors.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, Thomas Sounart, Henning Braunisch, William J. Lambert, Kaladhar Radhakrishnan, Shawna M. Liff, Mohammad Enamul Kabir, Omkar G. Karhade, Kimin Jun, Johanna M. Swan
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Publication number: 20240063544Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.Type: ApplicationFiled: October 31, 2023Publication date: February 22, 2024Applicant: Intel CorporationInventors: Jimin Yao, Robert L. Sankman, Shawna M. Liff, Sri Chaitra Jyotsna Chavali, William J. Lambert, Zhichao Zhang
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Patent number: 11870132Abstract: Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.Type: GrantFiled: May 9, 2022Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Sidharth Dalmia, Jonathan Jensen, Ozgur Inac, Trang Thai, William J. Lambert, Benjamin Jann
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Patent number: 11870163Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.Type: GrantFiled: March 25, 2022Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Jimin Yao, Robert L. Sankman, Shawna M. Liff, Sri Chaitra Jyotsna Chavali, William J. Lambert, Zhichao Zhang
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Publication number: 20230354508Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.Type: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Applicant: Intel CorporationInventors: Sidharth Dalmia, Zhenguo Jiang, William J. Lambert, Kirthika Nahalingam, Swathi Vijayakumar
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Patent number: 11804456Abstract: A microelectronics package, comprising a substrate comprising a first bondpad and a second bondpad over a dielectric. An inductor comprising at least one wire extends over the dielectric. The at least one wire has a first end coupled to the first bondpad and a second end coupled to the second bondpad, and an inductor core layer over the dielectric. The inductor core layer comprises a magnetic material. At least a portion of the inductor extends within the inductor core layer.Type: GrantFiled: August 21, 2018Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: William J. Lambert, Omkar Karhade, Martin Rodriguez, Gregorio R. Murtagian
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Patent number: 11699630Abstract: An apparatus is provided which comprises: one or more pads comprising metal on a first substrate surface, the one or more pads to couple with contacts of an integrated circuit die, one or more substrate layers comprising dielectric material, one or more conductive contacts on a second substrate surface, opposite the first substrate surface, the one or more conductive contacts to couple with contacts of a printed circuit board, one or more inductors on the one or more substrate layers, the one or more inductors coupled with the one or more conductive contacts and the one or more pads, and highly thermally conductive material between the second substrate surface and a printed circuit board surface, the highly thermally conductive material contacting the one or more inductors. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 14, 2022Date of Patent: July 11, 2023Assignee: Intel CorporationInventor: William J. Lambert
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Publication number: 20230096368Abstract: An inductor structure, a package substrate, an integrated circuit device, an integrated circuit device assembly and a method of fabricating the inductor structure. The inductor structure includes: an electrically conductive body; and a magnetic structure including a non-electrically-conductive magnetic material, wherein: one of the magnetic structure or the electrically conductive body wraps around another one of the magnetic structure or the electrically conductive body to form the inductor structure therewith; and at least one of the electrically conductive body or the magnetic structure has a granular microstructure including randomly distributed particles presenting substantially non-linear particle-to-particle boundaries with one another.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Aleksandar Aleksov, Adel Elsherbini, Johanna Swan, Feras Eid, Thomas L. Sounart, Henning Braunisch, Beomseok Choi, Krishna Bharath, Kaladhar Radhakrishnan, William J. Lambert
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Publication number: 20230095608Abstract: A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Adel Elsherbini, Aleksandar Aleksov, Feras Eid, Henning Braunisch, Thomas L. Sounart, Johanna Swan, Beomseok Choi, Krishna Bharath, William J. Lambert, Kaladhar Radhakrishnan
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Publication number: 20230097714Abstract: In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: William J. Lambert, Beomseok Choi, Krishna Bharath, Kaladhar Radhakrishnan, Adel Elsherbini
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Publication number: 20230095063Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Beomseok Choi, William J. Lambert, Krishna Bharath, Kaladhar Radhakrishnan, Adel Elsherbini, Henning Braunisch, Stephen Morein, Aleksandar Aleksov, Feras Eid
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Patent number: 11616283Abstract: Embodiments include an electronic package that includes a radio frequency (RF) front end. In an embodiment, the RF front end may comprise a package substrate and a first die attached to a first surface of the package substrate. In an embodiment, the first die may include CMOS components. In an embodiment, the RF front end may further comprise a second die attached to the first surface of the package substrate. In an embodiment, the second die may comprise amplification circuitry. In an embodiment, the RF front end may further comprise an antenna attached to a second surface of the package substrate. In an embodiment, the second surface is opposite from the first surface.Type: GrantFiled: September 5, 2018Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Omkar Karhade, William J. Lambert, Xiaoqian Li, Sidharth Dalmia
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Publication number: 20230088170Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die by solder interconnects, and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by non-solder interconnects.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Applicant: Intel CorporationInventors: Xavier Francois Brun, Sanka Ganesan, Holly Sawyer, William J. Lambert, Timothy A. Gosselin, Yuting Wang
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Patent number: 11608564Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.Type: GrantFiled: March 26, 2021Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: William J. Lambert, Mihir K Roy, Mathew J Manusharow, Yikang Deng
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Publication number: 20230082706Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.Type: ApplicationFiled: September 15, 2021Publication date: March 16, 2023Applicant: Intel CorporationInventors: Sanka Ganesan, William J. Lambert, Bharat Prasad Penmecha, Xavier Francois Brun