Abstract: Embodiments herein relate to a medical device for treating a cancerous tumor, the medical device having a first lead including a first wire and second wire; a second lead can include a third wire and fourth wire; and a first electrode in electrical communication with the first wire, a second electrode in electrical communication with the second wire, a third electrode in electrical communication with the third wire, and a fourth electrode in electrical communication with the fourth wire. The first and third electrodes form a supply electrode pair configured to deliver one or more electric fields to the cancerous tumor. The second and fourth electrodes form a sensing electrode pair configured to measure an impedance of the cancerous tumor independent of an impedance of the first electrode, the first wire, the third electrode, the third wire, and components in electrical communication therewith. Other embodiments are also included herein.

Abstract: A compiler and linker include multiple addressing mode resolvers that generate code to resolve a plurality of function calls that use different addressing modes. A first addressing mode is defined where a first address for first data is specified as an offset from a base pointer. A second, relative addressing mode is defined where a second address for second data is specified as an offset from an address of an instruction that references the second data. The generated code assures correct operation when functions with different addressing modes are included in the computer program. The generated code preserves a base pointer when executing a function that uses relative addressing, when needed. The compiler inserts one or more relocation markers that trigger certain functions in the linker. A linker resolves the relocation markers inserted by the compiler, and generates code, when needed, that handles a mismatch between addressing modes.

Abstract: A compiler and linker include multiple addressing mode resolvers that generate code to resolve a plurality of function calls that use different addressing modes. A first addressing mode is defined where a first address for first data is specified as an offset from a base pointer. A second, relative addressing mode is defined where a second address for second data is specified as an offset from an address of an instruction that references the second data. The generated code assures correct operation when functions with different addressing modes are included in the computer program. The generated code preserves a base pointer when executing a function that uses relative addressing, when needed. The compiler inserts one or more relocation markers that trigger certain functions in the linker. A linker resolves the relocation markers inserted by the compiler, and generates code, when needed, that handles a mismatch between addressing modes.

Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector operations that are reformatting-resistant, such as source instructions that do not have a corresponding reformatting operation, sink instructions that do not have a corresponding reformatting operation, a source instruction that is a scalar value, a sink instruction that may produce a scalar value, and an internal operation that depends on lanes being in a specified order. The ability to optimize vector instructions that are reformatting-resistant reduces the number of operations to improve the run-time performance of the code.

Abstract: A compiler and linker include multiple addressing mode resolvers that generate code to resolve a plurality of function calls that use different addressing modes. A first addressing mode is defined where a first address for first data is specified as an offset from a base pointer. A second, relative addressing mode is defined where a second address for second data is specified as an offset from an address of an instruction that references the second data. The generated code assures correct operation when functions with different addressing modes are included in the computer program. The generated code preserves a base pointer when executing a function that uses relative addressing, when needed. The compiler inserts one or more relocation markers that trigger certain functions in the linker. A linker resolves the relocation markers inserted by the compiler, and generates code, when needed, that handles a mismatch between addressing modes.

Abstract: A compiler and linker include multiple addressing mode resolvers that generate code to resolve a plurality of function calls that use different addressing modes. A first addressing mode is defined where a first address for first data is specified as an offset from a base pointer. A second, relative addressing mode is defined where a second address for second data is specified as an offset from an address of an instruction that references the second data. The generated code assures correct operation when functions with different addressing modes are included in the computer program. The generated code preserves a base pointer when executing a function that uses relative addressing, when needed. The compiler inserts one or more relocation markers that trigger certain functions in the linker. A linker resolves the relocation markers inserted by the compiler, and generates code, when needed, that handles a mismatch between addressing modes.

Abstract: Techniques are disclosed for managing vector element ordering. One technique includes setting one or more control bits that determine a vector element ordering and a vector element numbering, where the one or more control bits are stored in a machine status register or in a page table entry. The vector element ordering includes one of a big-endian mode and a little-endian mode, and the vector element numbering includes one of a big-endian mode and a little-endian mode. The technique includes reading the one or more control bits to determine a big-endian or a little-endian mode for the vector element ordering and for the vector element numbering. The technique also includes performing a vector operation in the determined mode for the vector element ordering and the determined mode for the vector element numbering.

Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector operations that are reformatting-resistant, such as source instructions that do not have a corresponding reformatting operation, sink instructions that do not have a corresponding reformatting operation, a source instruction that is a scalar value, a sink instruction that may produce a scalar value, and an internal operation that depends on lanes being in a specified order. The ability to optimize vector instructions that are reformatting-resistant reduces the number of operations to improve the run-time performance of the code.

Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector operations that are reformatting-resistant, such as source instructions that do not have a corresponding reformatting operation, sink instructions that do not have a corresponding reformatting operation, a source instruction that is a scalar value, a sink instruction that may produce a scalar value, and an internal operation that depends on lanes being in a specified order. The ability to optimize vector instructions that are reformatting-resistant reduces the number of operations to improve the run-time performance of the code.

Abstract: A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a bi-endian environment, wherein the processor architecture contains instructions with an inherent endian bias, along with at least one memory access instruction with a contrary endian bias. The compiler uses a code generation endian preference that matches the inherent computer system endian bias. The compiler generates instructions for vector instructions by determining whether the vector instruction has an endian bias that matches the code generation endian preference. When the endian bias of the vector instruction matches the code generation endian preference, the compiler generates one or more instructions for the vector instruction as normal.

Abstract: A stand alone input device can be a touch pad that provides touch inputs to an associated computing device. The input device can include a wedge-shaped base defining an inner cavity, a touch plate having a touch surface disposed over the inner cavity and configured to accept a touch input, cantilevered beams coupled to the wedge-shaped base and the touch plate and configured to deliver a force from the touch input, a haptic generator coupled to the cantilevered beams and configured to generate a haptic output in response to the touch input, an antenna component integrated within a wall of the wedge-shaped base and an antenna resonance cavity located within the inner cavity, and a switch assembly including a sliding component having a pin through a wedge-shaped base wall and a switch beam having a protrusion that engages multiple recesses located at a detent region on the sliding component.

Abstract: Techniques are disclosed for managing vector element ordering. One technique includes receiving an assembler command from a source file, wherein the assembler command indicates a vector element order for one or more subsequent machine instructions in the source file. The technique includes determining whether the vector element order comprises a big-endian (BE) order or a little-endian (LE) order. If the vector element order comprises a BE order, the technique includes assembling one or more subsequent machine instructions and placing the machine instructions in a BE section of a file. If the vector element order comprises a LE order, the technique includes assembling one or more subsequent machine instructions and placing the machine instructions in a LE section of the file.

Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector operations that are reformatting-resistant, such as source instructions that do not have a corresponding reformatting operation, sink instructions that do not have a corresponding reformatting operation, a source instruction that is a scalar value, a sink instruction that may produce a scalar value, and an internal operation that depends on lanes being in a specified order. The ability to optimize vector instructions that are reformatting-resistant reduces the number of operations to improve the run-time performance of the code.

Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector operations that are reformatting-resistant, such as source instructions that do not have a corresponding reformatting operation, sink instructions that do not have a corresponding reformatting operation, a source instruction that is a scalar value, a sink instruction that may produce a scalar value, and an internal operation that depends on lanes being in a specified order. The ability to optimize vector instructions that are reformatting-resistant reduces the number of operations to improve the run-time performance of the code.

Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector operations that are reformatting-resistant, such as source instructions that do not have a corresponding reformatting operation, sink instructions that do not have a corresponding reformatting operation, a source instruction that is a scalar value, a sink instruction that may produce a scalar value, and an internal operation that depends on lanes being in a specified order. The ability to optimize vector instructions that are reformatting-resistant reduces the number of operations to improve the run-time performance of the code.

Abstract: Two parties have three distinct viewpoints of their relationship, from which assumptions emerge and working hypotheses about how to manage their relationship. The system, device, and method described herein include using a mobile device for understanding face-to-face human interactions. The process includes using a mobile device for recording an interaction with one or more other persons, whereby one or more of the participants use the mobile device to describe their viewpoints of the interaction. The participants can use the mobile device to receive immediate feedback for analysis, to compare viewpoints, to examine how the viewpoints are arrived, and to explore the viewpoints' consequences for the participants' relationship.

Abstract: Techniques are disclosed for managing vector element ordering. One technique includes receiving an assembler command from a source file, wherein the assembler command indicates a vector element order for one or more subsequent machine instructions in the source file. The technique includes determining whether the vector element order comprises a big-endian (BE) order or a little-endian (LE) order. If the vector element order comprises a BE order, the technique includes assembling one or more subsequent machine instructions and placing the machine instructions in a BE section of a file. If the vector element order comprises a LE order, the technique includes assembling one or more subsequent machine instructions and placing the machine instructions in a LE section of the file.

Abstract: Techniques are disclosed for managing vector element ordering. One technique includes setting one or more control bits that determine a vector element ordering and a vector element numbering, where the one or more control bits are stored in a machine status register or in a page table entry. The vector element ordering includes one of a big-endian mode and a little-endian mode, and the vector element numbering includes one of a big-endian mode and a little-endian mode. The technique includes reading the one or more control bits to determine a big-endian or a little-endian mode for the vector element ordering and for the vector element numbering. The technique also includes performing a vector operation in the determined mode for the vector element ordering and the determined mode for the vector element numbering.

Abstract: Two parties have three distinct viewpoints of their relationship, from which assumptions emerge and working hypotheses about how to manage their relationship. The system, device, and method described herein include using a mobile device for understanding face-to-face human interactions. The process includes using a mobile device for recording an interaction with one or more other persons, whereby one or more of the participants use the mobile device to describe their viewpoints of the interaction. The participants can use the mobile device to receive immediate feedback for analysis, to compare viewpoints, to examine how the viewpoints are arrived, and to explore the viewpoints' consequences for the participants' relationship.

Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector instructions by eliminating one or more vector element reverse operations. The compiler can generate code that includes multiple vector element reverse operations that are inserted by the compiler to account for a mismatch between the endian bias of the instruction and the endian preference indicated by the programmer or programming environment. The compiler then analyzes the code and reduces the number of vector element reverse operations to improve the run-time performance of the code.