Abstract: A method for compensating for jitter during DDR3 delay line training may include using a computer or processor to perform the steps of executing a plurality of tests for each one of a plurality of delay values for an interconnect delay between a Double-Data-Rate Three (DDR3) memory controller and a DDR3 Synchronous Dynamic Random Access Memory (SDRAM); accumulating a plurality of test results for each plurality of tests for each one of the plurality of delay values; determining a plurality of final test results, where each final test result is associated with an accumulated plurality of test results; and determining a working window edge for the interconnect delay between the DDR3 memory controller and the DDR3 SDRAM utilizing the plurality of final test results.

Abstract: Methods and systems assess timing of PCI signals. A test mode is initiated within a host adapter board. A clock signal is generated for the host adapter board. PCI signals are generated within the host adapter board. One or more PCI signal lines of the host adapter board are electronically selected; and timing (e.g., slew rate and/or clock-to-signal valid) of the one or more PCI signal lines is assessed.

Abstract: Systems and methods for analyzing data passing between an SAS/SATA device and a plurality of other devices are presented. A system includes a plurality of physical interfaces configured for passing data between the SAS/SATA device and the other devices. The system also includes a test interface, or test PHY, configured for coupling to the physical interfaces for analysis of the data passing through those physical interfaces. The test PHY may be integrally configured with the SAS/SATA device and may substantially minimize alteration of characteristic impedance caused by external analysis of the data. The system may also include a multiplexer for selectively coupling the PHYs to the test PHY.

Abstract: Systems and methods for analyzing data transferred through an SPI data bus are presented. In one exemplary preferred embodiment of the invention, an SPI data probe imitates an SPI device coupled to the SPI data bus and receives data from the SPI data bus so that the data may be analyzed. The SPI data probe transfers the data to an analysis unit without substantially altering impedance more than the SPI device would. The SPI data probe includes connectors configured for coupling the probe to the SPI data bus and for coupling the probe to an analysis unit. The SPI data probe also includes circuitry that may buffer, compensate and deskew the data as an SPI device would.

Abstract: A signal testing implementation provides significant advantages over conventional signal testing techniques. According to an exemplary embodiment, an apparatus for enabling signal testing such as SCSI signal testing in a test configuration includes a portable cable environment having a plurality of cables exhibiting a plurality of lengths and impedances. A user can selectively connect any one of the cables between a host device such as a server and a target device such as a disk subsystem. Signal measurement connectors which are connectable to the portable cable environment may be provided. According to an embodiment, each of the signal measurement connectors includes one or more test measurement points to enable collection of signal testing results.

Abstract: Systems and methods for analyzing data transferred through an SPI data bus are presented. In one exemplary preferred embodiment of the invention, an SPI data probe imitates an SPI device coupled to the SPI data bus and receives data from the SPI data bus so that the data may be analyzed. The SPI data probe transfers the data to an analysis unit without substantially altering impedance more than the SPI device would. The SPI data probe includes connectors configured for coupling the probe to the SPI data bus and for coupling the probe to an analysis unit. The SPI data probe also includes circuitry that may buffer, compensate and deskew the data as an SPI device would.

Abstract: Systems and methods for analyzing data passing between an SAS/SATA device and a plurality of other devices are presented. A system includes a plurality of physical interfaces configured for passing data between the SAS/SATA device and the other devices. The system also includes a test interface, or test PHY, configured for coupling to the physical interfaces for analysis of the data passing through those physical interfaces. The test PHY may be integrally configured with the SAS/SATA device and may substantially minimize alteration of characteristic impedance caused by external analysis of the data. The system may also include a multiplexer for selectively coupling the PHYs to the test PHY.

Abstract: A method and apparatus for generating a CRC/parity error in network environment. A SCSI bus expander such as an Ultra320 bus expander or the like is added between a sending device and a receiving device. The sending device-receiving device pair may execute a training session to determine the skew compensation. During the training session, the SCSI bus expander may figure out timing differences due to skew and adjusts the timing of each data signal to compensate for skew. For each data signal, a compensated time may be obtained. The compensated time may then be modified through a JTAG port of the SCSI bus expander. The compensated times may be adjusted such that a CRC/parity error is generated on every I/O or just some I/Os to the receiving device. By intentionally generating a CRC/parity error, the response of the devices in the SCSI environment to a CRC/parity error may be evaluated during an input/output (I/O) test.