Abstract: A clock multiplexer circuit uses a delay element to detect a transition-free period in a first signal present on a D-input lead of an output latch. The output latch is then controlled to latch the stable value of the first signal, and to hold the value of the first signal on an output lead of the clock multiplexer circuit. The clock multiplexer circuit then controls a multiplexer of the clock multiplexer circuit to couple a second signal onto the D-input lead of the output latch. The clock multiplexer circuit then enables the output latch synchronously with respect to the second signal such that the output latch is made transparent at a time when the second signal on the D-input of the output latch is stable and not transitioning. The result is glitch free clock switching from the first signal to the second signal.

Abstract: A clock multiplexer circuit uses a delay element to detect a transition-free period in a first signal present on a D-input lead of an output latch. The output latch is then controlled to latch the stable value of the first signal, and to hold the value of the first signal on an output lead of the clock multiplexer circuit. The clock multiplexer circuit then controls a multiplexer of the clock multiplexer circuit to couple a second signal onto the D-input lead of the output latch. The clock multiplexer circuit then enables the output latch synchronously with respect to the second signal such that the output latch is made transparent at a time when the second signal on the D-input of the output latch is stable and not transitioning. The result is glitch free clock switching from the first signal to the second signal.

Abstract: Fast electromagnetic transient (EFT) events of short duration are often not detected by power-on reset circuitry of an integrated circuit (IC). A fault detector circuit involves many fault detectors. The fault detectors are distributed across the IC and may be embodied in spare cells left in a standard cell IC. Each fault detector is initialized with a digital logic value. The fault detector circuit is then controlled such that the digital logic value stored should not change if the IC is operated under normal operating conditions. An EFT event that is undetected by the power-on reset circuit may, however, cause one of the digital logic values stored in one of the fault detectors to switch. If the digital logic value stored in any one of the fault detectors switches, then a fault signal is provided to the power-on reset circuit that in turn resets the IC.

Abstract: A single shared processing path is used as contexts are switched during processing. Each unique context is processed using a corresponding unique pipeline. If a pipeline that is executing under one context stalls, processing is switched in the shared processing path to another pipeline that is executing under second context. New pipelines are enabled for execution by borrowing a clock cycle from the currently executing pipeline. In some cases contexts are assigned various relative priority levels. In one case a context switching microprocessor is used in a communication engine portion of a system-on-a-chip communication system.

Abstract: Bus access is arbitrated among modules connected to a common bus. Each module has a priority level and an arbitration number assigned to it. More than one module can have the same priority level. For each priority level, the arbitration numbers assigned are unique. When two or more modules attempt bus access at the same time, the one with the higher priority level wins access. If the priority levels are the same but one module has already accessed the bus, the module that has been waiting wins access. If the modules have the same priority level and have been waiting then the module with the highest arbitration number wins access.

Abstract: An arbitration unit contains a method of arbitration which includes distributed arbitration, a priority mechanism to support different classes of traffic, a unique arbitration ID bits for each module, a round robin arbitration within a given priority level to produce fair access to a bus 36, an arbitration timeout, and a bandwidth allocation between priority levels.