Abstract: A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information; connecting the fuse cell to the fuse read node for reading the information; and determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.

Abstract: A circuit may include a first switch to pre-charge a first voltage line to a first voltage for a first amount of time, such that the first voltage is an opposite polarity as compared to a second voltage coupled to the first voltage line when a first fuse is blown. The circuit may also include a second switch to pre-charge a second voltage line to a third voltage for the first amount of time, such that the third voltage is an opposite polarity as compared to a fourth voltage coupled to the second voltage line when a second fuse is blown. The circuit also includes a latch circuit to amplify a first voltage signal present on the first voltage line and amplify a second voltage signal present on the second voltage line after the first amount of time expires.

Abstract: A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information; connecting the fuse cell to the fuse read node for reading the information; and determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.

Abstract: A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information; connecting the fuse cell to the fuse read node for reading the information; and determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.

Abstract: A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information; connecting the fuse cell to the fuse read node for reading the information; and determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.

Abstract: An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor is coupled to the terminal and includes a first gate terminal coupled to receive a first select signal. The bias transistor is coupled between the substrate and a bias voltage terminal. The bias transistor has a second gate terminal and is operable to couple the bias voltage terminal to the substrate responsive to an assertion of a bias enable signal at the second gate terminal.

Abstract: An antifuse circuit includes a terminal, an antifuse, and a select transistor. The antifuse is coupled to the terminal and has an associated program voltage. The select transistor is coupled to the antifuse and has a gate terminal coupled to receive a first select signal. The select transistor operates in a snapback mode of operation in response to an assertion of the first select signal and the program voltage at the terminal.

Abstract: An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor is coupled to the terminal and includes a first gate terminal coupled to receive a first select signal. The bias transistor is coupled between the substrate and a bias voltage terminal. The bias transistor has a second gate terminal and is operable to couple the bias voltage terminal to the substrate responsive to an assertion of a bias enable signal at the second gate terminal.

Abstract: An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor is coupled to the terminal and includes a first gate terminal coupled to receive a first select signal. The bias transistor is coupled between the substrate and a bias voltage terminal. The bias transistor has a second gate terminal and is operable to couple the bias voltage terminal to the substrate responsive to an assertion of a bias enable signal at the second gate terminal.

Abstract: An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor is coupled to the terminal and includes a first gate terminal coupled to receive a first select signal. The bias transistor is coupled between the substrate and a bias voltage terminal. The bias transistor has a second gate terminal and is operable to couple the bias voltage terminal to the substrate responsive to an assertion of a bias enable signal at the second gate terminal.

Abstract: An antifuse circuit includes a terminal, an antifuse, and a select transistor. The antifuse is coupled to the terminal and has an associated program voltage. The select transistor is coupled to the antifuse and has a gate terminal coupled to receive a first select signal. The select transistor operates in a snapback mode of operation in response to an assertion of the first select signal and the program voltage at the terminal.

Abstract: A self propelled steerable vehicle for transporting a wheelchair bound passenger between two separate locations, such as between a terminal and an aircraft parked on a ramp, includes a lift assembly mounted on said vehicle for movement from a lowermost position to an operator selectable upper position. The vehicle is provided with an operator's compartment containing steering, braking, motive and lift assembly controls. An internal combustion engine powers a hydraulic system for both moving the vehicle and powering the lift assembly. A passenger's compartment carried by said lift assembly is provided with a pair of ramps which are movable from a loading position to a traveling position. In the loading position, hand rails are automatically extended. Gas cylinders between the hand rails and the ramp assist the operator is raising the ramps. In the traveling position, the ramps act as gates for the passenger compartment.