Abstract: Mitigation techniques can be used to reduce noise generated by wireless communication circuitry (e.g., near-field communication circuitry) in an electronic device including a display, touch, and wireless communication circuitry. In some examples, a touch screen can have a backplane including a mesh of routing traces connected to an array of chiplets. In some examples, the chiplets can repeat signals to prevent the accumulation of noise induced by an NFC coil. In some examples, the ratio between vertical and horizontal resistances of routing traces can be configured to mitigate noise induced by the coil. In some examples, the routing traces of the mesh can be configured to share a common geometric centroid. In some examples, a plurality of routing traces can be routed in a twisted pair configuration. In some examples, the routing traces and chiplets can be routed to minimize traversal through regions of relatively high electromagnetic field.

Abstract: An apparatus to facilitate hardware enhancements for double precision systolic support is disclosed. The apparatus includes matrix acceleration hardware having double-precision (DP) matrix multiplication circuitry including a multiplier circuits to multiply pairs of input source operands in a DP floating-point format; adders to receive multiplier outputs from the multiplier circuits and accumulate the multiplier outputs in a high precision intermediate format; an accumulator circuit to accumulate adder outputs from the adders with at least one of a third global source operand on a first pass of the DP matrix multiplication circuitry or an intermediate result from the first pass on a second pass of the DP matrix multiplication circuitry, wherein the accumulator circuit to generate an accumulator output in the high precision intermediate format; and a down conversion and rounding circuit to down convert and round an output of the second pass as final result in the DP floating-point format.

Abstract: Electronic displays and electronic devices including such electronic displays and antennas are provided for improved transmission of signals through circuitry of the electronic display. The electronic display may include multiple power supply tiles that are separated with non-conductive gaps to reduce circulation of eddy currents induced by the transmission signals. Moreover, voltage supply routing paths within the power supply tiles may be grouped to provide non-conductive gaps within the power supply tiles. Accordingly, the antenna may provide the transmission signals through the electronic display with improved efficiency based on reducing surface currents (e.g., eddy currents) on the electronic display.

Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.

Abstract: The present disclosure provides systems and methods to enable significant improvements in display systems utilizing projectors and a retro-reflective (RR) screen through use of transparent or semi-transparent RR material. An aspect of the present disclosure provides methods for optimization of optical properties of the RR material to achieve desired optical transparency parameters. Another aspect of the present disclosure provides methods for specific use cases for flexible, transparent and semi-transparent RR display systems.

Abstract: The present disclosure provides systems and methods to enable significant improvements in display systems utilizing projectors and a retro-reflective (RR) screen through use of transparent or semi-transparent RR material. An aspect of the present disclosure provides methods for optimization of optical properties of the RR material to achieve desired optical transparency parameters. Another aspect of the present disclosure provides methods for specific use cases for flexible, transparent and semi-transparent RR display systems.

Abstract: A remote control device comprises a housing cover configured to mate with a touch-enabled surface configured to receive input gestures, and a battery holder disposed between the housing cover and the touch-enabled surface. A first plurality of magnets is disposed in the housing cover. A second plurality of magnets is disposed in the battery holder. The first plurality of magnets in the housing cover is attracted to the second plurality of magnets in a first position of the housing cover relative to the battery holder. The first plurality of magnets in the housing cover is repelled from the second plurality of magnets in a second position of the housing cover relative to the battery holder. The first position and the second position share a rotational axis normal to the touch-enabled surface.

Abstract: A system and method for providing a user interface for live media content is described. A top portion of the user interface is populated with media content categories. A selection of a media content category from the media content categories is received. A bottom portion of the user interface is populated with at least one panel relating to the selection of media content category. A timeline comprising a progress indicator corresponding to a progress of a live media content associated with the at least one panel is generated in the user interface.

Abstract: A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

Abstract: A power optimization method of deriving gated circuitry in an integrated circuit (IC) is provided. A design description of the IC is received and analyzed. A state machine is identified based on the analysis. One or more candidate blocks are determined to be capable of being disabled. At least one of the candidate blocks is selected based on one or more states of the state machine. A gating circuit is inserted for gating the selected candidate block(s). In another embodiment of power optimization, one or more state machines are identified and a synthesized netlist is generated. One or more candidate blocks in the synthesized netlist are determined to be capable of being disabled. At least one of the candidate blocks is selected based on one or more states in the state machine, and a gating circuit is inserted for gating the selected candidate block(s).

Abstract: A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.

Abstract: A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

Abstract: Embodiments of the invention provide a circuit to implement an on-chip resistor with desired temperature coefficient behavior. In some embodiments, a circuit may comprise an amplifier, with a reference controlled by ratioed amounts of one or more positive temperature coefficient (TC+) and/or negative temperature coefficient (TC?) circuits, coupled to a controllable resistor device to control it as temperature changes to track the desired temperature coefficient behavior.

Abstract: A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

Abstract: A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.

Abstract: A method of routing a data packet in a communication system includes receiving a data packet at a first communication party operating in accordance with a first protocol. The method also includes adding a header to the data packet to produce modified data packet, the header including an identifier identifying the first protocol, first protocol information, an identifier identifying a second protocol, and second protocol information, and then sending the modified data packet to a second communication party operating in accordance with the second protocol through a first connection.

Abstract: An improved methodology and implementing system are provided in which a number of different user ID and password combinations are assigned to the user. Each combination is associated with a different service which may be requested by the user. When a user ID and password combination is uploaded from a terminal to a server, the server system compares the combination with a stored memory of associations to determine which of several possible services is being requested by the user. In one example, a server will respond to a first combination to enable normal processing of a money transaction at an ATM terminal, but will respond to a second combination to effect notification of authorities that a distress situation such as a robbery is occurring at the terminal.