Patents by Inventor William John Saiki
William John Saiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7939892Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.Type: GrantFiled: October 6, 2010Date of Patent: May 10, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Sang Thanh Nguyen, Vishal Sarin, Hung Q. Nguyen, William John Saiki, Loc B. Hoang
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Publication number: 20110022905Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.Type: ApplicationFiled: October 6, 2010Publication date: January 27, 2011Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Sang Thanh Nguyen, Vishal Sarin, Hung O. Nguyen, William John Saiki, Loc B. Hoang
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Patent number: 7831872Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.Type: GrantFiled: December 14, 2009Date of Patent: November 9, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Sang Thanh Nguyen, Vishal Sarin, Hung Q. Nguyen, William John Saiki, Loc B. Hoang
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Publication number: 20100091567Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.Type: ApplicationFiled: December 14, 2009Publication date: April 15, 2010Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Sang Thanh Nguyen, Vishal Sarin, Hung Q. Nguyen, William John Saiki, Loc B. Hoang
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Patent number: 7661041Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.Type: GrantFiled: December 10, 2007Date of Patent: February 9, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Sang Thanh Nguyen, Vishal Sarin, Hung Q. Nguyen, William John Saiki, Loc B. Hoang
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Publication number: 20090303803Abstract: A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different margins and verify levels.Type: ApplicationFiled: August 18, 2009Publication date: December 10, 2009Applicant: Silicon Storage Technology, Inc.Inventors: VISHAL SARIN, HIEU VAN TRAN, WILLIAM JOHN SAIKI
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Patent number: 7596037Abstract: A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different margins and verify levels.Type: GrantFiled: September 14, 2007Date of Patent: September 29, 2009Assignee: Silicon Storage Technology, Inc.Inventors: Vishal Sarin, Hieu Van Tran, William John Saiki
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Publication number: 20090096507Abstract: An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration.Type: ApplicationFiled: November 13, 2008Publication date: April 16, 2009Applicant: Silicon Storage Technology, Inc.Inventors: Feng Gao, Changyuan Chen, Vishal Sarin, William John Saiki, Hieu Van Tran, Dana Lee
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Publication number: 20090073770Abstract: A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different margins and verify levels.Type: ApplicationFiled: September 14, 2007Publication date: March 19, 2009Applicant: Silicon Storage Technology, Inc.Inventors: Vishal Sarin, Hieu Van Tran, William John Saiki
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Publication number: 20090067235Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.Type: ApplicationFiled: December 10, 2007Publication date: March 12, 2009Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Sang Thanh Nguyen, Vishal Sarin, Hung Q. Nguyen, William John Saiki, Loc B. Hoang
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Patent number: 7325177Abstract: A test circuit is sued to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.Type: GrantFiled: November 17, 2004Date of Patent: January 29, 2008Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Sang Thanh Nguyen, Vishal Sarin, Hung Q. Nguyen, William John Saiki, Loc B. Hoang
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Patent number: 7184345Abstract: A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.Type: GrantFiled: November 18, 2005Date of Patent: February 27, 2007Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Jack Edward Frayer, William John Saiki, Michael Stephen Briner
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Patent number: 7061295Abstract: An oscillator that can be used within a high voltage generation and regulation system for non-volatile memory. The system may comprise a charge pump that may have at least one pump and an oscillator. In one aspect the oscillator provides clock signals to the pump. The output of the oscillator may be disabled without turning off the clock generation. The oscillator may be a ring oscillator. In one aspect, the ring oscillator and the output stage may comprise inverters with a capacitor coupled to the output of the inverter. In one aspect, the ratio of the capacitors in the ring oscillator to the capacitor in the output stage determine the phase shift between the two clock signals. In another aspect, the capacitance of the capacitors are identical and a bias applied the ring oscillator and the output stage are radioed to adjust the phase between the two clock signals.Type: GrantFiled: November 16, 2004Date of Patent: June 13, 2006Assignee: Silicon Storage Technology, Inc.Inventors: William John Saiki, Hieu Van Tran, Sakhawat M. Khan
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Patent number: 7038960Abstract: A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.Type: GrantFiled: September 10, 2002Date of Patent: May 2, 2006Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Jack Edward Frayer, William John Saiki, Michael Stephen Briner
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Patent number: 7038538Abstract: An operational amplifier comprises multiple stages. A differential input stage that includes an adaptive high voltage differential pair generates up and down output currents in response to up and down input voltages. The differential input stage includes adaptive common input high voltage (HV) bias. An intermediate stage converts the up and down output currents into a first output voltage signal. The intermediate stage includes a folded cascode arrangement. The intermediate stage is biased by fixed voltage bias signals. The intermediate stage also includes unaffected slew rate stability compensation and a combined split stability compensation. An output stage includes a class AB source follower driver that generates a second output voltage signal in response to the first output voltage signal. The output stage is biased with an adaptive push-pull source follower output HV bias. The output stage includes feed-forward slew rate enhancement.Type: GrantFiled: February 26, 2003Date of Patent: May 2, 2006Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sakhawat M. Khan, William John Saiki
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Patent number: 6992937Abstract: A digital multilevel bit memory array system comprises regular memory arrays and redundant memory arrays. A regular y-driver corresponds to each memory array to read or write contents to a multilevel bit memory cell and compare the read cell content to reference voltage levels to determine the data stored in the corresponding memory cell. Likewise, similar functions are performed by the redundant y-driver circuit for the redundant memory array. During the verification of the contents of the memory cell, if the read voltage is outside a certain margin requirement for a level of the reference voltage, a signal is generated in real time so that data from the bad y-driver is not output and data from the redundant y-driver corresponding to the redundant memory array is read out. The memory array system may also include a fractional multilevel redundancy.Type: GrantFiled: July 28, 2003Date of Patent: January 31, 2006Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sakhawat M. Khan, William John Saiki, George J. Korsh
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Patent number: 6967524Abstract: A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.Type: GrantFiled: November 16, 2004Date of Patent: November 22, 2005Assignee: Silicon Storage Technology, Inc.Inventors: William John Saiki, Hieu Van Tran, Sakhawat M. Khan
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Patent number: 6885600Abstract: A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.Type: GrantFiled: September 10, 2002Date of Patent: April 26, 2005Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Jack Edward Frayer, William John Saiki, Michael Stephen Briner
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Patent number: 6867638Abstract: A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.Type: GrantFiled: January 10, 2002Date of Patent: March 15, 2005Assignee: Silicon Storage Technology, Inc.Inventors: William John Saiki, Hieu Van Tran, Sakhawat M. Khan
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Patent number: 6813194Abstract: A memory device includes an array of memory cells arranged in rows and columns with a portion of the rows of the memory cells being divided into segments. A global bias circuit generates a plurality of first bias currents. Each of a plurality of local bias networks includes a local bias circuit that generates a plurality of second bias currents in response to a corresponding one of the plurality of first bias currents, and includes a plurality of segment bias circuits that each generates a third bias current. Each segment bias circuit is adjacent to a corresponding segment of the memory cells. Each segment bias circuit provides a ground feedback signal to the local bias circuit, which adjusts the second bias current in response to the ground feedback signal. The segment bias circuits are disposed in geometric positions in the segments.Type: GrantFiled: January 10, 2002Date of Patent: November 2, 2004Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, William John Saiki