Abstract: A method and apparatus in a data processing system for protecting against a displacement of one type of cache line using a least recently used cache management process. A first member in a class of cache lines is selected as a substitute victim. The substitute victim is unselectable by the least-recently-used cache management process, and the substitute victim is associated with a second member in the class of cache lines. The substitute victim is replaced in response to a selection of the second member as a victim in response to a cache miss in the data processing system, wherein the second member remains in the class of cache lines.

Abstract: A method and system are disclosed for managing stored soft state information, such as the contents of cache memory and address translation information that are non-critical for executing a process within a processor. The soft states of idle processes are stored in system memory in virtual caches. Cache coherency of the soft states is maintained by snooping kill-type operations against the virtual caches in system memory.

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

Abstract: An I/O communication adapter receives from a processor core an I/O command referencing an effective address within an effective address space of the processor core that identifies a storage location. In response to receipt of the I/O command, the I/O communication adapter translates the effective address into a real address by reference to a translation data structure. The I/O communication adapter then accesses the storage location utilizing the real address to perform an I/O data transfer specified by the I/O command.

Abstract: A method of performing operations to a link stack including the step of performing a Pop operation from the link stack which includes the substeps of storing a first pointer value to the link stack, the first pointer value being the value of a pointer to the link stack before the Pop operation, and storing a first address including a first tag popped from the link stack. The method further includes the step of performing a Push operation to the link stack which includes the substeps of storing a second address including a second tag being Pushed into the link stack and storing a second pointer to the link stack, the second pointer being the value of the pointer to the link stack after the Push operation.

Abstract: An improved method and apparatus for selecting invalid members as victims in a least recently used cache system. An invalid cache line selection unit has an input connected to a cache directory and an output connected to a most recently used update logic. In response to a miss in the cache, an invalid cache line is identified from information in the cache directory by the invalid cache line selection unit. This invalid cache line is updated to be the next victim by the most recently used update logic, rather than attempting to override the current victim selection by a least recently used victim selection logic. The next victim also may be selected in response to a cache hit in which information from the cache directory also is read.

Abstract: A method and apparatus for managing cache lines in a data processing system. A special purpose register is employed in which this register may be manipulated by user code and operating system code to set preferences, such as a level 2 cache management policy preference for an application thread. These preferences may be dynamically set and an arbitration mechanism is employed to best satisfy preferences of multiple threads with a single aggregate preference. Members are represented using a least recently used tree. The least recent used tree has a set of nodes forming a path to member cache lines in a hierarchical structure. A state of a selected node is selectively biased within the set of nodes in the least recently used tree. At least one node on a level below the selected node is eliminated from being selected in managing the cache lines. In this manner, members can be biased against or for selection as victims when replacing cache lines in a cache memory.

Abstract: A method and apparatus in a data processing system for protecting against displacement of two types of cache lines using a least recently used cache management process. A first member in a class of cache lines is selected as a first substitute victim. The first substitute victim is unselectable by the least recently used cache management process, and the second substitute victim is associated with a selected member in the class of cache lines. A second member in the class of cache lines is selected as a second substitute victim. The second victim is unselectable by the least recently used cache management process, and the second substitute victim is associated with the selected member in the class of cache lines. One of the first or second substitute victims are replaced in response to a selection of the selected member as a victim when a cache miss occurs, wherein the selected member remains in the class of cache lines.

Abstract: A method and apparatus in a data processing system for protecting against a displacement of one type of cache line using a least recently used cache management process. A first member in a class of cache lines is selected as a substitute victim. The substitute victim is unselectable by the least-recently-used cache management process, and the substitute victim is associated with a second member in the class of cache lines. The substitute victim is replaced in response to a selection of the second member as a victim in response to a cache miss in the data processing system, wherein the second member remains in the class of cache lines.

Abstract: A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N−1)-bit error detection. In the illustrative embodiment, the ECC matrix has an odd number of bits set in each row thereof. In the case of an ECC protected mechanism such as a memory device, these properties facilitate the use of an inversion bit for correcting hard faults in the stored data. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array.

Abstract: A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N−1)-bit error detection. In the illustrative embodiment, the ECC matrix has an odd number of bits set in each row thereof. In the case of an ECC protected mechanism such as a memory device, these properties facilitate the use of an inversion bit for correcting hard faults in the stored data. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array.

Abstract: A hazard prediction array consists of an array of saturating counters. The array is indexed through a portion of the instruction address. At issue, the hazard prediction array is referenced and a prediction is made as to whether the current instruction or group of instructions is likely to encounter a flush. If the prediction is that it will flush, the instruction is not issued until it is the next instruction to complete. If the prediction is that the instruction will not flush, it is issued as normal. At completion time, the prediction array is updated with the actual flush behavior. When an instruction is predicted to flush and, thus, not issued until it is the next to complete, the predictor may be updated as if the instruction did not flush.

Abstract: A data processing system includes an instruction pipeline, including one or more execution units that execute instructions and an instruction sequencing unit that dispatches instructions to the execution units for execution. The data processing system further includes a memory controller for a memory containing an instruction trace log and an interconnect coupled to the instruction pipeline and to the memory controller. The interconnect transmits to the memory controller for storage in the instruction trace log instructions processed within the instruction pipeline.

Abstract: An integrated circuit, such as a processing unit, includes a substrate and integrated circuitry formed in the substrate. The integrated circuitry includes a processor core that executes instructions, an interconnect interface, coupled to the processor core, that supports communication between the processor core and a system interconnect external to the integrated circuit, and at least a portion of an external communication adapter, coupled to the processor core, that supports input/output communication via an input/output communication link.

Abstract: An I/O communication adapter receives from a processor core an I/O command referencing an effective address within an effective address space of the processor core that identifies a storage location. In response to receipt of the I/O command, the I/O communication adapter translates the effective address into a real address by reference to a translation data structure. The I/O communication adapter then accesses the storage location utilizing the real address to perform an I/O data transfer specified by the I/O command.

Abstract: A processing unit includes a processor core, an input/output (I/O) communication adapter coupled to the processor core, and a cache system coupled to the processor core and to the I/O communication adapter. The cache system including a cache array, a cache directory and a cache controller. The cache controller snoops I/O communication by the I/O communication adapter and, in response to snooping the I/O communication adapter performing an I/O data write of outgoing data in an exclusive state, invalidates corresponding data stored within the cache array.

Abstract: Execution of code within a processor is accelerated through hardware bypass of repetitive code sequences. In accordance with a preferred method, an instruction sequence including a plurality of instructions is executed within one or more execution units of a processor to generate and store a data result. The processor records instruction addresses and target addresses of selected instructions within the instruction sequence. After recording the instruction addresses and target addresses, any operation affecting the instruction sequence is detected. Thereafter, in response to detecting an intended execution of the instruction sequence by the processor, the processor bypasses execution of the plurality of instructions within the instruction sequence in response to failing to detect an operation affecting particular instructions within the instruction sequence after the recording.

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

Abstract: A method and system are disclosed for managing stored soft state information, such as the contents of cache memory and address translation information that are non-critical for executing a process within a processor. The soft states of idle processes are stored in system memory in virtual caches. Cache coherency of the soft states is maintained by snooping kill-type operations against the virtual caches in system memory.