Abstract: Audio processing apparatus in which a payload signal is inserted into a primary audio signal comprises a noise generator operable to generate a noise signal in dependence on the payload signal; a level detector for detecting a signal level of the primary signal; a modulator for respectively increasing or decreasing the level of the noise signal in response to an increase or a decrease of the detected signal level of the primary audio signal, to generate a modulated noise signal; a combiner for combining the primary signal and the modulated noise signal; and a signal delay arrangement; the modulator operating with respect to the signal delay arrangement so that a decrease in the level of the noise signal is time-advanced with respect to the corresponding decrease in the signal level of the primary audio signal.

Abstract: A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the events.

Abstract: A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the said events.

Abstract: Digital signal processing apparatus for adding signals generates a plurality of intermediate digital signals from a plurality of input digital signals, each intermediate digital signal composed of a respective additive combination of the input digital signals, and includes a signal selector for selecting one of the intermediate digital signals, an output digital signal being dependent on the selected intermediate digital signal.

Abstract: A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A, B of the system in dependence upon the event to be indicated, the pairs of memory locations A, B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A, B; processing the data read from each pair of memory locations A, B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor.