Abstract: The present invention describes a new method for implementing highly available data-parallel-operations on a computational grid. This new method provides high availability after a server fails or the grid experiences a partial network failure. The present invention invokes the data parallel operation's method on selected objects stored in partitions within a highly available distributed cache. It thereby takes advantage of the use of highly available data partitions implemented by the distributed cache as a means for reliably tracking the progress of method invocations within a data parallel operation even after a server or network failure occurs. Using the cache's partitions as the basis for tracking enables the present invention's method to restart method invocations and thereby ensure completion of the data-parallel operation. It also uses a completion object within the cache to ensure that completion of the data parallel operation is detected and reported in a highly available manner.

Abstract: The invention comprises a software-based communications architecture and associated software methods for establishing and maintaining a common membership among a cluster of multiple, cooperating computers (called hosts). The invention incorporates the use of nearest neighbor and overlapping heartbeat connections between clustered computers that are logically organized in a linear or multi-dimensional array. This arrangement of heartbeat connections has two principal advantages. First it keeps the cluster membership highly available after host failures because hosts can quickly detect and recover from another host's failure without partitioning the membership. Second, it enables the cluster membership to scale to large numbers (e.g., hundreds) of computers because the computational and message passing overhead per host to maintain the specified heartbeat connections is fixed and the underlying physical network is allowed to scale.

Abstract: A new network load balancing/firewall node for use in a system including multiple network load balancing/firewall nodes is disclosed. The network load balancing/firewall applies bi-directional load balancing affinity with regard to requests from external clients and corresponding responses from internal network servers. An external network load balancing adapter executes a load-balancing algorithm to determine whether a received client request is accepted by the network load balancing/firewall node. A firewall utility processes the received client request and maintains state information associated with the received client request. An internal network load balancing adapter executes a complementary load-balancing algorithm simultaneously on each network load balancing/firewall node to ensure that the same network load balancing/firewall node accepts a response from an internal network server corresponding to the received client request.

Abstract: A cluster of computers typically establishes a quorum, i.e., a software method for establishing agreement, to coordinate access to shared resources, such as a shared data store, in applications that must recover from the failure of one or more computers or their associated components. Prior art which associates a single quorum with an entire cluster, has inherent overheads that limit the size of the cluster to a small number of computers. The present invention comprises a scalable, software-based architecture for implementing a quorum mechanism to coordinate the actions of a cluster of computers. In contrast to prior art, the present invention advantageously encapsulates the quorum in a software construct, called a quorum object, which is disassociated from the cluster as a whole and spans a designated subset of the cluster's membership.

Abstract: A new network load balancing/firewall node for use in a system including multiple network load balancing/firewall nodes is disclosed. The network load balancing/firewall applies bi-directional load balancing affinity with regard to requests from external clients and corresponding responses from internal network servers. An external network load balancing adapter executes a load-balancing algorithm to determine whether a received client request is accepted by the network load balancing/firewall node. A firewall utility processes the received client request and maintains state information associated with the received client request. An internal network load balancing adapter executes a complementary load-balancing algorithm simultaneously on each network load balancing/firewall node to ensure that the same network load balancing/firewall node accepts a response from an internal network server corresponding to the received client request.

Abstract: An I/O processor includes an execution unit (EU), a register file, an I/O bus sequencer and a local bus sequencer. The EU decodes an ACCESS instruction having a pointer to a parameter register comprised of: a number of fields for storing a sequencer code identifying one of the sequencers; a logical byte specifying a location in memory to be addressed and valid and block bits; a reply register set pointer to a register set in the register file designated to receive a reply to the ACCESS instruction; and, a length field specifying the location and length of a data block in the register file from which data is to be obtained. A data pointer is generated by taking the logical byte in the parameter register and passing it through a register set mapper to produce a register file physical address. The valid bit of the logical byte is turned off as it is translated by the register the mapper so that the bus sequencer can take control over the corresponding register set.

Abstract: An I/O processor for controlling data transfer between a local bus and an I/O bus. An Execution Unit, an I/O bus sequencer, and a local bus sequencer are connected to a register file. The register file is uniformly addressed and each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer have read/write access to the register file. The register file is comprised of a plurality of register sets. The Execution Unit includes a programmed processor which is programmed to allocate the register sets among tasks running on the processor by passing register-set descriptors between the tasks in the form of messages. The local bus sequencer includes a packet-oriented multiprocessor bus, there being a variable number of bytes in each of the packets. The I/O sequencer includes logic for multibyte sequencing of data at a bus-dependent data rate between the I/O bus and the register file. Each of the tasks includes a task frame, each task frame including register-set pointers.

Abstract: An I/O bus sequencer for providing a data path between an execution Unit (EU-10), a register file (14) and devices connected to a bus (28). A programmable logic array (PLA-18) stores a program which controls a service table (20). The service table includes a plurality of entries divided into fields. One of the fields when decoded instructs the PLA as to what kind of operation the bus sequencer is to perform. Line selection (priority) logic (22) connected to I/O request lines (30) and to the service table (20) determines which service table entry the PLA is to use. A bus interface connected to the I/O bus ports (26) and to the PLA (18) routes data between the I/O bus ports (26) and the register file (14), entries of which are controlled by use of register sets. The service table fields include register set descriptors for storing the status of register set buffers.