Patents by Inventor William L. Larson

William L. Larson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Passivated magneto-resistive bit structure and passivation method therefor
    Patent number: 7427514
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: September 23, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Harry Liu, Lonny Berg, William L. Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • Varactor with improved tuning range
    Patent number: 7169679
    Abstract: A varactor has a plurality of alternating P? wells and N+ regions formed in a silicon layer. Each of the P? wells forms a first N+/P? junction with the N+ region on one of its side and a second N+/P? junction with the N+ region on the other of its sides. A gate oxide is provided over each of the P? wells, and a gate silicon is provided over each of the gate oxides. The potential across the gate silicons and the N+ regions controls the capacitance of the varactor.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: January 30, 2007
    Assignee: Honeywell International Inc.
    Inventors: Cheisan J. Yue, Mohammed A. Fathimulla, Eric E. Vogt, William L. Larson
  • Methods of increasing write selectivity in an MRAM
    Patent number: 6992918
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: January 31, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • Passivated magneto-resistive bit structure
    Publication number: 20040227244
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Application
    Filed: June 21, 2004
    Publication date: November 18, 2004
    Applicant: Micron Technology, Inc.
    Inventors: Harry Liu, Lonny Berg, William L. Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • Passivated magneto-resistive bit structure
    Patent number: 6806546
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: October 19, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Harry Liu, Lonny Berg, William L Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • Methods of increasing write selectivity in an MRAM
    Patent number: 6791856
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • Methods of increasing write selectivity in an MRAM
    Patent number: 6756240
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: June 29, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • Passivated magneto-resistive bit structure and passivation method therefor
    Publication number: 20040091634
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Application
    Filed: August 22, 2003
    Publication date: May 13, 2004
    Applicant: Micron Technology, Inc.
    Inventors: Harry Liu, Lonny Berg, William L. Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • METHODS OF INCREASING WRITE SELECTIVITY IN AN MRAM
    Publication number: 20040082082
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Application
    Filed: July 7, 2003
    Publication date: April 29, 2004
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • Methods of increasing write selectivity in an MRAM
    Publication number: 20040004878
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Application
    Filed: July 7, 2003
    Publication date: January 8, 2004
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • Passivated magneto-resistive bit structure and passivation method therefor
    Patent number: 6623987
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: September 23, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Harry Liu, Lonny Berg, William L. Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • Varactor with improved tuning range
    Publication number: 20030127691
    Abstract: A varactor has a plurality of alternating P− wells and N+ regions formed in a silicon layer. Each of the P− wells forms a first N+/P− junction with the N+ region on one of its side and a second N+/P− junction with the N+ region on the other of its sides. A gate oxide is provided over each of the P− wells, and a gate silicon is provided over each of the gate oxides. The potential across the gate silicons and the N+ regions controls the capacitance of the varactor.
    Type: Application
    Filed: January 7, 2002
    Publication date: July 10, 2003
    Applicant: Honeywell International Inc.
    Inventors: Cheisan J. Yue, Mohammed A. Fathimulla, Eric E. Vogt, William L. Larson
  • Methods of increasing write selectivity in an MRAM
    Publication number: 20030086321
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Application
    Filed: December 20, 2002
    Publication date: May 8, 2003
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • MRAM architectures for increased write selectivity
    Patent number: 6522574
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: February 18, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • MRAM architecture using offset bits for increased write selectivity
    Patent number: 6424561
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: July 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • MRAM architectures for increased write selectivity
    Patent number: 6424564
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: July 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • Passivated magneto-resistive bit structure
    Publication number: 20020085412
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Application
    Filed: February 14, 2002
    Publication date: July 4, 2002
    Inventors: Harry Liu, Lonny Berg, William L. Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • Passivated magneto-resistive bit structure and passivation method therefor
    Publication number: 20020080645
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Application
    Filed: January 24, 2002
    Publication date: June 27, 2002
    Applicant: Micron Technology, Inc.
    Inventors: Harry Liu, Lonny Berg, William L. Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • Passivated magneto-resistive bit structure and passivation method therefor
    Patent number: 6392922
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subject to oxidation or corrosion are protected. In one embodiment a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: May 21, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Harry Liu, Lonny Berg, William L. Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • MRAM architectures for increased write selectivity
    Publication number: 20020012268
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Application
    Filed: September 26, 2001
    Publication date: January 31, 2002
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu