Abstract: A method and apparatus for evaluating and rendering parametric curves such as non-uniform rational b-spline (NURBS) curves. NURBS data consisting of control point data, knot values and other data defining a curve is stored in system memory as a sequence of records such that successive spans of the curve are defined by successive individual data records in conjunction with a predetermined number of immediately preceding data records of the sequence. A graphics control processor transforms the control point data from modelling coordinates to view coordinates, converts the transformed control point data to homogeneous coordinates, and generates parameter points along the curve. Parallel floating point processors simultaneously evaluate the homogeneous coordinates of the curve at each parameter point along the curve using the Cox-de Boor procedure. A further floating point processor converts the homogeneous coordinates to geometric coordinates for subsequent rendering and display of the curve.

Abstract: In a computer graphics display system, a method and processor are disclosed for drawing one of a concave polygon, self-intersecting polygon and polygon with polygonal hole. Pursuant to the method, a mask buffer organized into an M.times.N plurality of addressable constituent pixels is used. The method includes the steps of: masking the pixels of the mask buffer corresponding to the boundary of the polygon and drawing the pixels in the frame buffer of the display system corresponding to the boundary of the polygon; masking the pixels in the mask buffer corresponding to the interior of the polygon while preserving the masked pixels in the mask buffer corresponding to the polygon boundary; and drawing the pixels in the frame buffer corresponding to the interior of the polygon with reference to the masked polygon interior pixels in the mask buffer.

Abstract: A method and apparatus for evaluating and rendering parametric surfaces. The apparatus includes a system memory connected to a graphics control processor, which is connected to local memory, and then connected in a pipelined arrangement to a plurality of parallel floating point processors, another floating point processor, a clipping processor and a frame buffer.