Abstract: An atomic instruction is executed without the use of a dedicated atomic unit. A store instruction is transmitted from a front-end of one of a plurality of processors to a write-cache to cause the write-cache to obtain exclusive access to a control memory of a shared resource. A first signal is then transmitted to the front end of the processor indicating that the write-cache has obtained exclusive access to the control memory of the shared source. At least one next instruction is executed, and a second signal is transmitted from the front end to the write cache indicating that execution of the at least one next instruction has been completed. Data from the write cache is stored in the control memory of the shared resource in response to the second signal transmitted to the write cache.

Abstract: A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing pipeline of the microprocessor in a fashion similar to the instruction which caused the miss (the "miss instruction"). The help instructions use the source operands of the miss instruction to form the miss address, thereby providing the fill address using the same elements which are used to calculate cache access addresses. In one embodiment, a fill help instruction and a bypass help instruction are generated. The fill help instruction provides the input address to the data cache during the clock cycle in which the fill data arrives. The appropriate row of the data cache is thereby selected for storing the fill data. The bypass help instruction is dispatched to arrive in a second pipeline stage different from the stage occupied by the fill help instruction.

Abstract: A significant reduction in the latency between the time the addressed components of memory are ready and the time addressed data is available to the address components of memory is achieved by processing the raw address information faster than the addition used in the prior art. XOR memory addressing replaces the addition of the base and offset address components with an XOR operation, eliminating carry propagation and reducing overall latency. In another embodiment, a sum-addressed memory (SAM) also eliminates the carry propagation and thus reduce the latency while providing the correct base+offset index to access the memory word line corresponding to the correct addition; thus a SAM causes no XOR duplicate problems.

Abstract: A parallel signal bus for conveying a plurality of logic signals with reduced Miller effect capacitance includes adjacent, parallel signal lines with inverting buffer amplifiers whose respective positions are staggered both longitudinally along the signal lines and latitudinally with respect to their adjacent signal lines. With such a staggered configuration, the resulting Miller effect capacitance which would otherwise result from adjacent signal lines being driven at opposing polarities is reduced, on average, by approximately half.