Patents by Inventor William M. Clark, Jr.
William M. Clark, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7008873Abstract: Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.Type: GrantFiled: March 23, 2005Date of Patent: March 7, 2006Assignees: HRL Laboratories, LLC, Raytheon CompanyInventors: Lap-Wai Chow, William M. Clark, Jr., James P. Baukus
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Patent number: 6979606Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.Type: GrantFiled: August 7, 2003Date of Patent: December 27, 2005Assignees: HRL Laboratories, LLC, Raytheon CompanyInventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, James P. Baukus
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Patent number: 6940764Abstract: A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling-a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.Type: GrantFiled: March 12, 2002Date of Patent: September 6, 2005Assignee: HRL Laboratories LLCInventors: William M. Clark, Jr., James P. Baukus, Lap-Wai Chow
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Patent number: 6924552Abstract: A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.Type: GrantFiled: October 14, 2003Date of Patent: August 2, 2005Assignees: HRL Laboratories, LLC, PromtekInventors: James P. Baukus, Lap-Wai Chow, William M. Clark, Jr., Paul Ou Yang
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Patent number: 6919600Abstract: A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.Type: GrantFiled: February 26, 2004Date of Patent: July 19, 2005Assignee: HRL Laboratories, LLCInventors: James P. Baukus, Lap-Wai Chow, William M. Clark, Jr.
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Patent number: 6897535Abstract: Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.Type: GrantFiled: May 14, 2003Date of Patent: May 24, 2005Assignee: HRL Laboratories, LLCInventors: Lap-Wai Chow, William M. Clark, Jr., James P. Baukus
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Patent number: 6893916Abstract: An integrated circuit structure for MOS-type devices including a silicon substrate of a first conductivity type; a first gate insulating regions selectively placed over the silicon substrate of the first conductivity tape; a first polycrystalline silicon layer selectively placed over the silicon substrate of the first conductivity type; a second gate insulating regions selectively placed over the first gate insulating regions and the first polycrystalline silicon layer; a second polycrystalline silicon layer selectively placed over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the first polycrystalline silicon layer and in contact therewith; and second buried silicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the second polycrystalline silicon layer and insulateType: GrantFiled: July 14, 2003Date of Patent: May 17, 2005Assignee: HRL Laboratories, LLCInventors: James P. Baukus, Lap-Wai Chow, William M. Clark, Jr.
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Patent number: 6815816Abstract: A camouflaged interconnection for interconnecting two spaced-apart implanted regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first implanted region forming a conducting channel between the two spaced-apart implanted regions, the conducting channel being of the same common conductivity type and bridging a region between the two spaced-apart regions, and a second implanted region of opposite conductivity to type, the second implanted region being disposed between the two spaced-apart implanted regions of common conductivity type and over lying the conducting channel to camouflage the conducting channel from reverse engineering.Type: GrantFiled: October 25, 2000Date of Patent: November 9, 2004Assignee: HRL Laboratories, LLCInventors: William M. Clark, Jr., James P. Baukus, Lap-Wai Chow
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Patent number: 6791191Abstract: A device adapted to protect integrated circuits from reverse engineering comprising a part looking like a via connecting two metal layers, but in fact attached only to one metal layer and spaced from the other. Having such “trick” via would force a reverse engineer to think there is a connection where there is none. A method for fabricating such device.Type: GrantFiled: January 24, 2001Date of Patent: September 14, 2004Assignee: HRL Laboratories, LLCInventors: Lap-Wai Chow, James P. Baukus, William M. Clark, Jr.
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Patent number: 6774413Abstract: An integrated circuit structure for MOS-type devices including a silicon substrate of a first conductivity type; a first gate insulating regions selectively placed over the silicon substrate of the first conductivity type; a first polycrystalline silicon layer selectively placed over the silicon substrate of the first conductivity type; a second gate insulating regions selectively placed over the first gate insulating regions and the first polycrystalline silicon layer; a second polycrystalline silicon layer selectively placed over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the first polycrystalline silicon layer and in contact therewith; and second buried silicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the second polycrystalline silicon layer and insulateType: GrantFiled: June 15, 2001Date of Patent: August 10, 2004Assignee: HRL Laboratories, LLCInventors: James P. Baukus, Lap-Wai Chow, William M. Clark, Jr.
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Patent number: 6740942Abstract: A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.Type: GrantFiled: June 15, 2001Date of Patent: May 25, 2004Assignee: HRL Laboratories, LLC.Inventors: James P. Baukus, Lap-Wai Chow, William M. Clark, Jr.
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Publication number: 20040047188Abstract: A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling-a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.Type: ApplicationFiled: June 20, 2003Publication date: March 11, 2004Inventors: William M. Clark ,Jr, James P. Baukus, Lap-Wai Chow
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Patent number: 6613661Abstract: An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.Type: GrantFiled: June 29, 2000Date of Patent: September 2, 2003Assignee: Hughes Electronics CorporationInventors: James P. Baukus, William M. Clark, Jr., Lap-Wai Chow, Allan R. Kramer
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Patent number: 6459629Abstract: A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.Type: GrantFiled: May 3, 2001Date of Patent: October 1, 2002Assignee: HRL Laboratories, LLCInventors: William M. Clark, Jr., James P. Baukus, Lap-Wai Chow
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Patent number: 6294816Abstract: An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.Type: GrantFiled: May 29, 1998Date of Patent: September 25, 2001Assignee: Hughes Electronics CorporationInventors: James P. Baukus, William M. Clark, Jr., Lap-Wai Chow, Allan R. Kramer
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Patent number: 6117762Abstract: A method and apparatus for protecting semiconductor integrated circuits from reverse engineering. Semiconductor active areas are formed on a substrate. A silicide layer is formed both over at least one active area of the semiconductor active areas and over a selected substrate area for interconnecting the at least one active area with another area through the silicide area formed on the selected substrate area. In a preferred embodiment a silicide layer formed on a first active area is interconnectingly merged laterally with a silicide layer formed on a second active area through the silicide layer formed on the selected substrate area.Type: GrantFiled: April 23, 1999Date of Patent: September 12, 2000Assignees: HRL Laboratories, LLC, Hughes Electronics CorporationInventors: James P. Baukus, Lap-Wai Chow, William M. Clark, Jr.
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Patent number: 6064110Abstract: An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants in the substrate rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads over the transistor array, with a uniform pattern of heavily doped implant taps from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.Type: GrantFiled: February 3, 1999Date of Patent: May 16, 2000Assignee: Hughes Electronics CorporationInventors: James P. Baukus, Lap Wai Chow, William M. Clark, Jr.
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Patent number: 5973375Abstract: Connections between implanted regions in a semiconductor substrate, such as the sources or drains of adjacent transistors, are made by buried conductive implants rather than upper level metalizations. The presence or absence of a connection between two implanted regions is camouflaged by implanting a conductive buried layer of the same doping conductivity as the implanted regions when a connection is desired, and a field implant of opposite conductivity to the implanted regions when no connection is desired, and forming steps into the substrate at the boundaries of the buried layer or field implant that mask the steps formed between different conductivity regions during a selective etch by a reverse engineer. The masking steps are preferably formed by field oxide layers that terminate at the boundaries of the buried layers and field implants.Type: GrantFiled: June 6, 1997Date of Patent: October 26, 1999Assignee: Hughes Electronics CorporationInventors: James P. Baukus, Lap-Wai Chow, William M. Clark, Jr.
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Patent number: 5930663Abstract: An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants in the substrate rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads over the transistor array, with a uniform pattern of heavily doped implant taps from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.Type: GrantFiled: May 11, 1998Date of Patent: July 27, 1999Assignee: Hughes Electronics CorporationInventors: James P. Baukus, Lap Wai Chow, William M. Clark, Jr.
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Patent number: 5871848Abstract: A binary, boron-based alloy as a source for field-emission-type, ion-beam generating devices, wherein boron predominates in the alloy, preferably with a presence of about 60 atomic percent. The other constituent in the alloy is selected from the group of elements consisting of nickel, palladium and platinum. Predominance of boron in these alloys, during operation, promotes combining of boron with trace impurities of carbon in the alloys to form B.sub.4 C and thus to promote wetting of an associated carbon support substrate.Type: GrantFiled: October 6, 1997Date of Patent: February 16, 1999Assignee: Oregon Graduate Institute of Science & TechnologyInventors: Michael J. Bozack, Lynwood W. Swanson, Anthony E. Bell, William M. Clark Jr., Mark W. Utlaut, Edmund K. Storms