Patents by Inventor William M. Hiatt

William M. Hiatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230106554
    Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 6, 2023
    Inventors: William M. Hiatt, Ross S. Dando
  • Patent number: 11476160
    Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: William M. Hiatt, Ross S. Dando
  • Patent number: 11177175
    Abstract: Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: William M. Hiatt, Kyle K. Kirby
  • Patent number: 11075146
    Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Rick C. Lake, William M. Hiatt
  • Publication number: 20210005514
    Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.
    Type: Application
    Filed: August 12, 2020
    Publication date: January 7, 2021
    Inventors: William M. Hiatt, Ross S. Dando
  • Publication number: 20200219793
    Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.
    Type: Application
    Filed: December 20, 2019
    Publication date: July 9, 2020
    Inventors: Warren M. Farnworth, Rick C. Lake, William M. Hiatt
  • Patent number: 10541192
    Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: January 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Rick C. Lake, William M. Hiatt
  • Publication number: 20180342477
    Abstract: Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.
    Type: Application
    Filed: August 6, 2018
    Publication date: November 29, 2018
    Inventors: William M. Hiatt, Kyle K. Kirby
  • Publication number: 20180304411
    Abstract: Systems and methods for forming apertures in microfeature workpieces are disclosed herein. In one embodiment, a method includes directing a laser beam toward a microfeature workpiece to form an aperture and sensing the laser beam pass through the microfeature workpiece in real time. The method can further include determining a number of pulses of the laser beam and/or an elapsed time to form the aperture and controlling the laser beam based on the determined number of pulses and/or the determined elapsed time to form a second aperture in the microfeature workpiece.
    Type: Application
    Filed: July 2, 2018
    Publication date: October 25, 2018
    Inventors: Charles M. Watkins, William M. Hiatt
  • Patent number: 10010977
    Abstract: Systems and methods for forming apertures in microfeature workpieces are disclosed herein. In one embodiment, a method includes directing a laser beam toward a microfeature workpiece to form an aperture and sensing the laser beam pass through the microfeature workpiece in real time. The method can further include determining a number of pulses of the laser beam and/or an elapsed time to form the aperture and controlling the laser beam based on the determined number of pulses and/or the determined elapsed time to form a second aperture in the microfeature workpiece.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Charles M. Watkins, William M. Hiatt
  • Publication number: 20170323828
    Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.
    Type: Application
    Filed: July 27, 2017
    Publication date: November 9, 2017
    Inventors: William M. Hiatt, Ross S. Dando
  • Publication number: 20170320154
    Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.
    Type: Application
    Filed: July 24, 2017
    Publication date: November 9, 2017
    Inventors: Warren M. Farnworth, Rick C. Lake, William M. Hiatt
  • Publication number: 20170301639
    Abstract: Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.
    Type: Application
    Filed: May 1, 2017
    Publication date: October 19, 2017
    Inventors: William M. Hiatt, Kyle K. Kirby
  • Patent number: 9737947
    Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: August 22, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Rickie C. Lake, William M. Hiatt
  • Patent number: 9653420
    Abstract: Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: May 16, 2017
    Assignee: Micron Technology, Inc.
    Inventors: William M. Hiatt, Kyle K. Kirby
  • Patent number: 9607930
    Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: March 28, 2017
    Assignee: Micron Technologies, Inc.
    Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt
  • Publication number: 20170008129
    Abstract: Systems and methods for forming apertures in microfeature workpieces are disclosed herein. In one embodiment, a method includes directing a laser beam toward a microfeature workpiece to form an aperture and sensing the laser beam pass through the microfeature workpiece in real time. The method can further include determining a number of pulses of the laser beam and/or an elapsed time to form the aperture and controlling the laser beam based on the determined number of pulses and/or the determined elapsed time to form a second aperture in the microfeature workpiece.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Charles M. Watkins, William M. Hiatt
  • Patent number: 9452492
    Abstract: Systems and methods for forming apertures in microfeature workpieces are disclosed herein. In one embodiment, a method includes directing a laser beam toward a microfeature workpiece to form an aperture and sensing the laser beam pass through the microfeature workpiece in real time. The method can further include determining a number of pulses of the laser beam and/or an elapsed time to form the aperture and controlling the laser beam based on the determined number of pulses and/or the determined elapsed time to form a second aperture in the microfeature workpiece.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: September 27, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Charles M. Watkins, William M. Hiatt
  • Publication number: 20160247747
    Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 25, 2016
    Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt
  • Patent number: 9343368
    Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: May 17, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt