Abstract: A device for protecting an integrated circuit (IC) against electrostatic discharge (ESD) includes a self-triggered silicon controlled rectifier (STSCR) coupled across the internal supply potentials of the integrated circuit. The STSCR exhibits a snap-back in its current versus voltage characteristic which is triggered at a predetermined voltage during an ESD event. As large voltages build up across the chip capacitance, the predetermined voltage of the SCR is triggered at a potential which is sufficiently low to protect the internal junctions of the IC from destructive reverse breakdown. The STSCR comprises a pnpn semiconductor structure which includes a n-well disposed in a p-substrate. A first n+ region and a p-type region are both disposed in the n-well. The n+ and p-type regions are spaced apart and electrically connected to form the anode of the SCR.

Abstract: An MOS dynamic random-access memory (RAM) realizable as a 64K RAM is disclosed. Single transistor cells employing capacitive storage are coupled to folded bit-line halves. These bit-line halves are connected to sense amplifiers employing cross-coupled transistors. Boosting means employing a variable capacitance are coupled to the bit-line halves to boost the potential on a line during reading. The capacitor associated with each of the memory cells is coupled to a potential which is greater than the power supply potential. This plate potential is substantially constant and independent of power supply variations and is internally generated. The dummy cells employed within the RAM are charged in a unique manner to a substantially constant potential which does not vary with power supply variations.