Patents by Inventor William M. Zevin
William M. Zevin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8493801Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.Type: GrantFiled: August 9, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Daniel M. Dreps, Kevin C. Gower, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann, James A. Mossman, Michael A. Sorna, Robert B. Tremaine, William M. Zevin
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Patent number: 8400845Abstract: Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.Type: GrantFiled: January 6, 2011Date of Patent: March 19, 2013Assignee: International Business Machines CorporationInventors: Lydia M. Do, William M. Zevin
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Publication number: 20120300564Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.Type: ApplicationFiled: August 9, 2012Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel M. Dreps, Kevin C. Gower, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann, James A. Mossman, Michael A. Sorna, Robert B. Tremaine, William M. Zevin
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Patent number: 8284621Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.Type: GrantFiled: February 15, 2010Date of Patent: October 9, 2012Assignee: International Business Machines CorporationInventors: Daniel M. Dreps, Kevin C. Gower, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann, James A. Mossman, Michael A. Sorna, Robert B. Tremaine, William M. Zevin
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Publication number: 20120176850Abstract: Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.Type: ApplicationFiled: January 6, 2011Publication date: July 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lydia M. Do, William M. Zevin
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Publication number: 20110199843Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.Type: ApplicationFiled: February 15, 2010Publication date: August 18, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel M. Dreps, Kevin C. Gower, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann, James A. Mossman, Michael A. Sorna, Robert B. Tremaine, William M. Zevin
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Patent number: 5737520Abstract: Methods and associated apparatus for analyzing and presenting captured state logic data including memory accesses by an intelligent I/O interface device and an attached computer system. The data analysis and display of the present invention aids an engineer in locating data corruption failures in a system. The heuristic analysis of the methods of the present invention locate and identify buffers accessed within the captured state logic data and buffer descriptors accessed within the captured state logic data despite the time dispersion thereof. The buffers and buffer descriptors located and identified within the captured state logic data are displayed on a computer display screen in a manner to more effectively assist an engineer in locating a root cause of data corruption than was possible with prior methods devoid of the analysis of the present invention.Type: GrantFiled: September 3, 1996Date of Patent: April 7, 1998Assignee: Hewlett-Packard Co.Inventors: Robert D. Gronlund, Brian A. Willette, William M. Zevin
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Patent number: 5491720Abstract: A method and system in a data communications system for automatically determining a data communication device type and a transmission speed associated with the data communication device type. An incoming communication is detected on a transmission line, and transmit and receive hardware are connected to the transmission line. Next, a sequence of different signals in either a first communication protocol or a second communication protocol are transmitted from a first data communication device via a transmission line. The transmission line is then monitored for a response signal from a second data communication device. The response signal is initiated from the second data communication device in response to receipt of a particular signal within the transmitted sequence of different signals.Type: GrantFiled: May 21, 1992Date of Patent: February 13, 1996Assignee: International Business Machines CorporationInventors: Gordon T. Davis, Judith M. Linger, Baiju D. Mandalia, John C. Sinibaldi, William M. Zevin, Karl-Heinz Ziegenhain
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Patent number: 5263054Abstract: An apparatus for efficient computation of a demodulation process on a digital signal processor for a sampled signal, which includes programming a digital signal processor to apply the sampled signal to an interpolating filter to add interpolation samples to the sampled signal, to search the sampled signal for a threshold crossing associated with a start bit, performing a linear interpolation to find a point where the threshold crossing occurs when a threshold crossing is detected, responsive to determining the point of the threshold crossing, determining a center of a start bit when the point of the threshold crossing has been determined, calculating a supplemental delay, and determining center points for subsequent of data bits utilizing the supplemental delay period from the center of the start bit.Type: GrantFiled: May 21, 1992Date of Patent: November 16, 1993Assignee: International Business Machines CorporationInventors: Gordon T. Davis, Baiju D. Mandalia, John C. Sinibaldi, William M. Zevin