Patents by Inventor William Martin Snelgrove
William Martin Snelgrove has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955170Abstract: A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.Type: GrantFiled: August 21, 2023Date of Patent: April 9, 2024Assignee: UNTETHER AI CORPORATIONInventors: Katsuyuki Sato, William Martin Snelgrove, Saijagan Saijagan, Joseph Francis Rohlman
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Patent number: 11941405Abstract: An example device includes a plurality of computational memory banks. Each computational memory bank of the plurality of computational memory banks includes an array of memory units and a plurality of processing elements connected to the array of memory units. The device further includes a plurality of single instruction, multiple data (SIMD) controllers. Each SIMD controller of the plurality of SIMD controllers is contained within at least one computational memory bank of the plurality of computational memory banks. Each SIMD controller is to provide instructions to the at least one computational memory bank.Type: GrantFiled: July 27, 2023Date of Patent: March 26, 2024Assignee: UNTETHER AI CORPORATIONInventors: William Martin Snelgrove, Darrick John Wiebe
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Patent number: 11934482Abstract: A processing device includes a two-dimensional array of processing elements, each processing element including an arithmetic logic unit to perform an operation. The device further includes interconnections among the two-dimensional array of processing elements to provide direct communication among neighboring processing elements of the two-dimensional array of processing elements. A processing element of the two-dimensional array of processing elements is connected to a first neighbor processing element that is immediately adjacent the processing element in a first dimension of the two-dimensional array. The processing element is further connected to a second neighbor processing element that is immediately adjacent the processing element in a second dimension of the two-dimensional array.Type: GrantFiled: August 3, 2023Date of Patent: March 19, 2024Assignee: UNTETHER AI CORPORATIONInventor: William Martin Snelgrove
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Patent number: 11881872Abstract: A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.Type: GrantFiled: April 29, 2022Date of Patent: January 23, 2024Assignee: UNTETHER AI CORPORATIONInventor: William Martin Snelgrove
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Publication number: 20240021237Abstract: A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.Type: ApplicationFiled: June 21, 2022Publication date: January 18, 2024Inventors: Katsuyuki SATO, William Martin SNELGROVE, Saijagan SAIJAGAN, Joseph Francis ROHLMAN
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Publication number: 20230420040Abstract: A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.Type: ApplicationFiled: August 21, 2023Publication date: December 28, 2023Inventors: Katsuyuki SATO, William Martin SNELGROVE, Saijagan SAIJAGAN, Joseph Francis ROHLMAN
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Publication number: 20230409338Abstract: An example device includes a plurality of computational memory banks. Each computational memory bank of the plurality of computational memory banks includes an array of memory units and a plurality of processing elements connected to the array of memory units. The device further includes a plurality of single instruction, multiple data (SIMD) controllers. Each SIMD controller of the plurality of SIMD controllers is contained within at least one computational memory bank of the plurality of computational memory banks. Each SIMD controller is to provide instructions to the at least one computational memory bank.Type: ApplicationFiled: July 27, 2023Publication date: December 21, 2023Inventors: William Martin SNELGROVE, Darrick John WIEBE
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Publication number: 20230395142Abstract: A low-power static random access memory (SRAM) is set forth which includes a cache memory function without requiring a special bit cell, and which realizes robust read and write operation without any write assist circuit at 16 nm or below FinFET technology. The SRAM comprises a half-Vdd precharge 6T SRAM cell array for robust operation at low supply voltage at 16 nm or below, and with cacheable dynamic flip-flop based differential amplifier referred to as a main amplifier (MA). Prior art 6T SRAM cell arrays use Vdd or Vdd-Vth precharge schemes, and have separate read and write amplifiers. The SRAM set forth uses one main amplifier only, which is connected to the bit line (BL) through a transmission gate. The main amplifiers functions as a read amplifier, write amplifier, and a cache memory.Type: ApplicationFiled: June 21, 2022Publication date: December 7, 2023Inventors: Katsuyuki SATO, William Martin SNELGROVE, Saijagan SAIJAGAN
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Publication number: 20230395141Abstract: A low-power static random access memory (SRAM) is set forth which includes a cache memory function without requiring a special bit cell, and which realizes robust read and write operation without any write assist circuit at 16 nm or below FinFET technology. The SRAM comprises a half-Vdd precharge 6 T SRAM cell array for robust operation at low supply voltage at 16 nm or below, and with cacheable dynamic flip-flop based differential amplifier referred to as a main amplifier (MA). Prior art 6 T SRAM cell arrays use Vdd or Vdd-Vth precharge schemes, and have separate read and write amplifiers. The SRAM set forth uses one main amplifier only, which is connected to the bit line (BL) through a transmission gate. The main amplifiers functions as a read amplifier, write amplifier, and a cache memory.Type: ApplicationFiled: August 21, 2023Publication date: December 7, 2023Inventors: Katsuyuki SATO, William Martin SNELGROVE, Saijagan SAIJAGAN
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Publication number: 20230376563Abstract: A processing device includes a two-dimensional array of processing elements, each processing element including an arithmetic logic unit to perform an operation. The device further includes interconnections among the two-dimensional array of processing elements to provide direct communication among neighboring processing elements of the two-dimensional array of processing elements. A processing element of the two-dimensional array of processing elements is connected to a first neighbor processing element that is immediately adjacent the processing element in a first dimension of the two-dimensional array. The processing element is further connected to a second neighbor processing element that is immediately adjacent the processing element in a second dimension of the two-dimensional array.Type: ApplicationFiled: August 3, 2023Publication date: November 23, 2023Inventor: William Martin SNELGROVE
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Publication number: 20230367739Abstract: A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.Type: ApplicationFiled: July 20, 2023Publication date: November 16, 2023Inventors: William Martin SNELGROVE, Jonathan SCOBBIE
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Publication number: 20230229450Abstract: An example device includes a plurality of computational memory banks. Each computational memory bank of the plurality of computational memory banks includes an array of memory units and a plurality of processing elements connected to the array of memory units. The device further includes a plurality of single instruction, multiple data (SIMD) controllers. Each SIMD controller of the plurality of SIMD controllers is contained within at least one computational memory bank of the plurality of computational memory banks. Each SIMD controller is to provide instructions to the at least one computational memory bank.Type: ApplicationFiled: March 27, 2023Publication date: July 20, 2023Inventors: William Martin SNELGROVE, Darrick John WIEBE
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Patent number: 11614947Abstract: An example device includes a plurality of computational memory banks. Each computational memory bank of the plurality of computational memory banks includes an array of memory units and a plurality of processing elements connected to the array of memory units. The device further includes a plurality of single instruction, multiple data (SIMD) controllers. Each SIMD controller of the plurality of SIMD controllers is contained within at least one computational memory bank of the plurality of computational memory banks. Each SIMD controller is to provide instructions to the at least one computational memory bank.Type: GrantFiled: August 31, 2018Date of Patent: March 28, 2023Assignee: UNTETHER AI CORPORATIONInventors: William Martin Snelgrove, Darrick Wiebe
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Publication number: 20230069360Abstract: A system and method for enhancing C*RAM, improving its performance for known applications such as video processing but also making it well suited to low-power implementation of neural nets. The required computing engine is decomposed into banks of enhanced C*RAM each having a SIMD controller, thus allowing operations at several scales simultaneously. Several configurations of suitable controllers are discussed, along with communication structures and enhanced processing elements.Type: ApplicationFiled: November 10, 2022Publication date: March 2, 2023Inventors: William Martin SNELGROVE, Darrick WIEBE
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Publication number: 20230004522Abstract: A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.Type: ApplicationFiled: September 12, 2022Publication date: January 5, 2023Inventors: William Martin SNELGROVE, Jonathan SCOBBIE
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Patent number: 11514294Abstract: A system and method for enhancing C*RAM, improving its performance for known applications such as video processing but also making it well suited to low-power implementation of neural nets. The required computing engine is decomposed into banks of enhanced C*RAM each having a SIMD controller, thus allowing operations at several scales simultaneously. Several configurations of suitable controllers are discussed, along with communication structures and enhanced processing elements.Type: GrantFiled: February 23, 2018Date of Patent: November 29, 2022Assignee: UNTETHER AI CORPORATIONInventors: William Martin Snelgrove, Darrick Wiebe
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Patent number: 11468002Abstract: A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.Type: GrantFiled: February 26, 2021Date of Patent: October 11, 2022Assignee: UNTETHER AI CORPORATIONInventors: William Martin Snelgrove, Jonathan Scobbie
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Publication number: 20220263525Abstract: A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.Type: ApplicationFiled: April 29, 2022Publication date: August 18, 2022Inventor: William Martin SNELGROVE
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Publication number: 20220171829Abstract: A processing device includes a two-dimensional array of processing elements, each processing element including an arithmetic logic unit to perform an operation. The device further includes interconnections among the two-dimensional array of processing elements to provide direct communication among neighboring processing elements of the two-dimensional array of processing elements. A processing element of the two-dimensional array of processing elements is connected to a first neighbor processing element that is immediately adjacent the processing element in a first dimension of the two-dimensional array. The processing element is further connected to a second neighbor processing element that is immediately adjacent the processing element in a second dimension of the two-dimensional array.Type: ApplicationFiled: February 18, 2022Publication date: June 2, 2022Inventor: William Martin SNELGROVE
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Patent number: 11342944Abstract: A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.Type: GrantFiled: September 23, 2020Date of Patent: May 24, 2022Assignee: UNTETHER AI CORPORATIONInventor: William Martin Snelgrove