Abstract: A vertically oriented thermal processor for processing batches of semiconductor wafers held within a processing chamber. The processing chamber is contained within a processing vessel. A furnace liner surrounds the processing vessel in spaced relationship. A flow path for cooling fluid is supplied between the furnace liner and an inner wall of the furnace heater. The flow occurs through end and base segments forming part of the furnace heating enclosure. The end and base segments have interior ports which communicate with a manifold chamber. The manifold chamber is advantageously divided into inner and outer chambers by shields which reflect radiant heat. The inner and outer manifold chambers are connected by manifold connecting passages formed between the shields.