Abstract: Data processing apparatus includes a storage circuit or memory, and an addressing circuit for identifying word locations within the storage circuit or memory into and from which a plurality of information items are to be written and read, respectively. A translating circuit is provided for successively shifting, in a write mode of operation, at least a portion of each information item so that it is stored in the storage circuit in a manner that the stored information item in each word location has a bit order different from that order of any other information item as stored in the storage circuit. In a read mode of operation, the translating or de-skewing circuit shifts the information items as read out from the storage circuit in a direction opposite to that imparted during the writing mode.

Abstract: Data processing apparatus includes a storage circuit or memory, and an addressing circuit for identifying word locations within the storage circuit into and from which a plurality of information items are to be written and read, respectively. Further, there is included an encoding circuit for encoding at least a part of each information item in one-out-of-n code, illustratively. In turn, the encoded part is successively shifted by a shift circuit so that it is stored in the storage circuit in a manner that the stored information in each word location has a bit order different from that order of any other information item as stored in the storage circuit. A translating or de-skewing circuit is provided for shifting the encoded data items as read out from the storage circuit in a direction opposite to that imparted by the first noted shift circuit.