Abstract: A system and method for allowing peers to exchange messages with other peers independently of their network location in a peer-to-peer environment. Messages may be transparently routed, potentially traversing partitions (e.g. firewalls and NATs), and using different protocols to reach the destination peers. In one embodiment, any peer node may serve as a relay peer that allows peers inside a partition to have a presence outside the partition and provides a mechanism for peers outside partitions to discover and communicate with peers inside the partitions. In one embodiment, a relay peer may maintain information on routes to other peers and assist in relaying messages to other peers. In one embodiment, any peer may query a relay peer for route information. In one embodiment, messages may include routing information as part of their payloads.

Abstract: A system and method for providing advertisements in a peer-to-peer networking environment is described. In one embodiment, the peer-to-peer protocols may use advertisements to describe and publish the existence of peer resources. An advertisement may be defined as a structured, language neutral metadata structure that names, describes, and publishes the existence of a peer-to-peer platform resource, such as a peer, a peer group, a pipe, or a service. In one embodiment, user-defined advertisement subtypes (for example, using XML schemas) may be formed from these basic types. A peer in a peer-to-peer network may publish a resource advertisement to make the resource corresponding to the advertisement available to other peers on the network. Peers may discover published advertisements by broadcasting discovery query messages. Other peers may respond to discovery query messages by sending response messages that may include advertisements.

Abstract: A processor includes logic for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB), a load buffer asynchronous interface, an external memory management unit (MMU) interface, and others. A processor includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, “pollution”, or “cross-talk” between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.

Abstract: N instruction class (IClass) fields, m branch prediction (BRPD) and k next fetch address fields are added to each instruction set of n instructions of a cache line of an instruction cache, where m and k are less than or equal to n. The BRPD and NFAPD fields of a cache line are initialized in accordance to a pre-established initialization policy of a branch and next fetch address prediction algorithm while the cache line is first brought into the instruction cache. The sets of IClasses, BRPDS, and NFAPDs of a cache line are accessed concurrently with the corresponding sets of instructions of the cache line. One BRPD and one NFAPD is selected from the set of BRPDs and NFAPDs corresponding to the selected set of instructions. The selected BRPD and NFAPD are updated in accordance to a pre-established update policy of the branch and next fetch address prediction algorithm when the actual branch direction and next fetch address are resolved.

Abstract: A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.

Abstract: One embodiment of the present invention provides a system that efficiently emulates sub-instructions in a very long instruction word (VLIW) processor. The system operates by receiving an exception condition during execution of a VLIW instruction within a VLIW program. This exception condition indicates that at least one sub-instruction within the VLIW instruction requires emulation in software or software assistance. In processing this exception condition, the system emulates the sub-instructions that require emulation in software and stores the results. The system also selectively executes in hardware any remaining sub-instructions in the VLIW instruction that do not require emulation in software. The system finally combines the results from the sub-instructions emulated in software with the results from the remaining sub-instructions executed in hardware, and resumes execution of the VLIW program.

Abstract: A processor includes a “four-dimensional” register structure in which register file structures are replicated by N for vertical threading in combination with a three-dimensional storage circuit. The multi-dimensional storage is formed by constructing a storage, such as a register file or memory, as a plurality of two-dimensional storage planes.

Abstract: A processor includes a thread switching control logic that performs a fast thread-switching operation in response to an L1 cache miss stall. The fast thread-switching operation implements one or more of several thread-switching methods. A first thread-switching operation is “oblivious” thread-switching for every N cycle in which the individual flip-flops locally determine a thread-switch without notification of stalling. The oblivious technique avoids usage of an extra global interconnection between threads for thread selection. A second thread-switching operation is “semi-oblivious” thread-switching for use with an existing “pipeline stall” signal (if any). The pipeline stall signal operates in two capacities, first as a notification of a pipeline stall, and second as a thread select signal between threads so that, again, usage of an extra global interconnection between threads for thread selection is avoided.

Abstract: The invention relates to a computer system and method for fetching a next instruction. In one embodiment, a computer system includes an instruction cache, a next fetch address register, and a fetch unit. The instruction cache includes an instruction array for storing a plurality of processor instructions and a next address fetch array for storing at least one next fetch address. Each next fetch address associated with at least one of the processor instructions stored in the instruction array and indicating a location of a processor instruction to be fetched. In another embodiment, an apparatus includes a first device configured to fetch a first instruction stored in an instruction cache, a second device configured to unconditionally store a next fetch address associated with the first instruction, and a third device configured to unconditionally fetch a second instruction stored at a location indicated by the stored next fetch address.

Abstract: In summary, the present invention is a multithreaded computer system having a memory that stores a plurality of objects and a plurality of procedures. The system uses a first global hashing procedure to service requests for the hashcodes of objects that do not have hashcodes, a local object-specific hashing procedure to service requests for hashcodes that have a recently generated hashcode, and a second global hashing procedure to service requests for the hashcodes of objects that have their hashcodes stored with the object. The global object hashing procedure has instructions for creating for each object a local object-specific hashing procedure. The local object hashing procedure includes as private data a hashcode and instructions for retrieving the hashcode. The second global hashing procedure includes instructions for retrieving the hashcode from the object.

Abstract: Elimination of traps and atomics in thread synchronization is provided. In one embodiment, a processor includes a lock cache. The lock cache holds a value that corresponds to or identifies a computer resource only if a current thread executing on the processor owns the computer resource. A lock cache operation (e.g., a lockcachecheck instruction) determines whether a value identifying a computer resource is cached in the lock cache and returns a first predetermined value if the value identifying the computer resource is cached in the lock cache. Otherwise, a second predetermined value is returned.

Abstract: A processor method and apparatus. The processor has an execution pipeline, a register file and a controller. The execution pipeline is for executing an instruction and has a first stage for generating a first result and a last stage for generating a final result. The register file is for storing the first result and the final result. The controller makes the first result stored in the register file available in the event that the first result is needed for the execution of a subsequent instruction. By storing the result of the first stage in the register file, the length of the execution pipeline is reduced from that of the prior art. Furthermore, logic required for providing inputs to the execution pipeline is greatly simplified over that required by the prior art.

Abstract: A hardware virtual machine instruction processor directly executes virtual machine instructions that are processor architecture independent. The hardware processor has high performance; is low cost; and exhibits low power consumption. The hardware processor is well suited for portable applications. These applications include, for example, an Internet chip for network appliances, a cellular telephone processor, other telecommunications integrated circuits, or other low-power, low-cost applications such as embedded processors, and portable devices.

Abstract: An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and a minimum array size boundary value. The array boundary checking apparatus of the invention includes an associative memory element that stores and retrieves a plurality of array bound values. Each one of the plurality of array bound values is associated with one of the plurality of array access instructions. An input section simultaneously compares the array access instruction identifier with at least a portion of each of the stored array reference entries, wherein the array access instruction identifier identifies an array access instruction. An output section is configured to provide as an array bounds output values one of the plurality of array bound values stored in one of the plurality of memory locations of the associated memory element.

Abstract: A computer processor includes a number of register pairs LOCKADDR/LOCKCOUNT. In each pair, the LOCKADDR/LOCKCOUNT register is to hold a value that identifies a lock for a computer resource. When a lock instruction issues, the corresponding LOCKCOUNT register is incremented. When an unlock instruction issues, the corresponding LOCKCOUNT register is decremented. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. This scheme provides fast locking and unlocking in many frequently occurring situations. In some embodiments, the LOCKCOUNT registers are omitted, and the lock is freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header which includes a pointer to a class structure. The class structure is aligned on a 4-byte boundary, and therefore two LSBs of the pointer to the class structure are zero and are not stored in the header.

Abstract: In a system and method for managing repeated lock requests to synchronize an object with a particular thread, each lockable object has a lock datum and each thread can repeatedly request a lock for an object without knowing whether the thread is already synchronized with the object. Associated with each thread are a pair of locking registers and a pair of stack data structures. The registers reference the last object whose lock was acquired by the thread and contain a redundancy count indicating the number of consecutive lock requests for the object. The stack data structures contain references to other objects that are currently synchronized with the thread and an associated redundancy count for each such object. A locking procedure acquires the lock of an object only if a reference to the object is not contained in the registers or the stack data structures.

Abstract: A computer system and associated method for executing a plurality of threads of execution with reduced memory space requirements. The computer system comprises a memory, an execution controller, and a data compressor. The execution controller controls execution of the threads such that the threads are executable and unexecutable at different times. The execution controller also stores uncompressed into available space in the run-time memory execution data of the threads when the execution data is generated. The data compressor compresses the uncompressed execution data of compressible ones of the threads that are unexecutable. As a result, space is made available in the run-time memory. The data compressor also decompresses in available space in the run-time memory the compressed execution data of decompressible ones of the threads so that the decompressible ones of the threads may be executed after becoming executable.

Abstract: In summary, the present invention is a multithreaded computer system having a memory that stores a plurality of objects and a plurality of procedures. Each object has a lock status of locked or unlocked, and includes a data pointer to a data structure. The system uses a global object locking procedure to service lock requests on objects that have never been locked as well as objects that have not recently been locked, and uses a local object-specific locking procedure to service lock requests on locked objects and objects that have been recently locked. The global object locking procedure has instructions for changing a specified unlocked object's lock status to locked, and for creating for each specified object a local object locking procedure. The local object locking procedure includes a lock data subarray for storing the object's lock data and instructions for updating a specified object's stored lock data.

Abstract: A compiler requires normal exceptions that are throwable by a method to be either explicitly declared or else "caught" by appropriate exception handlers in the method to be compiled. This ensures that all normal exceptions thrown will be handled by a programmer specified exception handler. The compiler inspects all instructions in a specified method that throw exceptions and all instructions that invoke other methods, and determines whether each type of exception throwable by those instructions and invocable methods is (A) a serious exception (i.e., not a normal exception), (B) is caught by an enclosing exception handler, or (C) is explicitly declared in the method header of the specified method. If any throwable exception cannot be so categorized, that means the throwable exception is a normal exception that is not caught by an enclosing exception and is not explicitly declared in the method header, which means that the method to be compiled is not well formed.

Abstract: A register window file method and apparatus is disclosed. A register file is formed from a plurality of registers. The registers are grouped into a plurality of logical windows. Window selection logic selects among the logical windows and thereby limits access at any given time to the selected logical window. Because access is limited to only one window at a time, an individual register can be selected by specifying its virtual register number. Therefore, there is no need to translate from virtual address numbers to physical address numbers when accessing registers. This means that virtual register number to physical register number translation logic of the prior art is no longer required. Thus, the area on the integrated circuit chip formerly occupied by the translation logic is no longer required. Furthermore, the translation delays per instruction introduced by the translation logic are also eliminated. Moreover, each register only shares read and write lines with the other registers of its window.