Patents by Inventor William Neifert

William Neifert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9542513
    Abstract: The disclosure contains descriptions of various methods and systems for accelerating the execution of a virtual prototype simulation. Acceleration may be achieved, for example, by providing two or more redundant virtual communication paths for access made by virtual models of a virtual prototype of a hardware design to provide for both accelerated access transactions and time-accurate access transactions. A model having such redundant virtual communication paths is referred to herein as a “multimode model.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 10, 2017
    Assignee: ARM LIMITED
    Inventors: Brian Scott Sylvester, William Neifert, Joseph Tatham, Matt Grasse, Ronald Scott Maxwell
  • Publication number: 20150039282
    Abstract: The disclosure contains descriptions of various methods and systems for accelerating the execution of a virtual prototype simulation. Acceleration may be achieved, for example, by providing two or more redundant virtual communication paths for access made by virtual models of a virtual prototype of a hardware design to provide for both accelerated access transactions and time-accurate access transactions. A model having such redundant virtual communication paths is referred to herein as a “multimode model.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: Carbon Design Systems, Inc.
    Inventors: Brian Scott Sylvester, William Neifert
  • Publication number: 20060085176
    Abstract: A system-level description that specifies functions performed by the components and interactions thereamong is divided into a plurality of functional blocks, each corresponding to a component. At least one of the functional blocks is selectively replaced with an optimized equivalent functional block, and the functional blocks and the at least one optimized equivalent functional block are interconnected in a manner consistent with the system-level description.
    Type: Application
    Filed: October 14, 2004
    Publication date: April 20, 2006
    Inventors: Matthew Bellantoni, William Neifert, Andrew Ladd, Matthew Grasse, Mark Kostick, Aron Atkins
  • Publication number: 20050228627
    Abstract: A system-level simulation of hardware devices, each of which may have different timing requirements, utilizes one or more master objects and update objects (e.g., a clock object) in order to coordinate the device simulations. The master object may, for example, advance the update objects according to one or more criteria and then instruct an object representing a hardware device to execute.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 13, 2005
    Inventors: Matthew Bellantoni, William Neifert, Andrew Ladd, Matthew Grasse, Mark Kostick
  • Publication number: 20050228628
    Abstract: A system-level simulation of hardware devices utilizes interconnection objects to facilitate communication between a simulated device and the system, or between different simulated devices. A device may send output data to the interconnection object and/or receive input from the interconnection object. Additionally, the interconnection object may have some data-validation capability for incoming and outgoing data.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 13, 2005
    Inventors: Matthew Bellantoni, William Neifert, Andrew Ladd, Matthew Grasse, Mark Kostick
  • Publication number: 20050229170
    Abstract: Integration of a system-level simulation with one or more hardware device simulations is accomplished using a mapping layer, which allows the system-level simulation to interact with the hardware device simulation at a pin level, an object level, and an abstract level. The overall simulation may operate with respect to a clock or timing device or it may operate with respect to transactions.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 13, 2005
    Inventors: Matthew Bellantoni, William Neifert, Andrew Ladd, Matthew Grasse, Mark Kostick
  • Publication number: 20050055675
    Abstract: System and methods for generating a software object that simulates the operation of a hardware device from a register transfer level description of the device written in a hardware description language, such as Verilog. The invention uses global analysis techniques (i.e., analysis of the design of the electronic device as a whole) to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).
    Type: Application
    Filed: November 7, 2003
    Publication date: March 10, 2005
    Inventors: William Neifert, Joshua Marantz, Richard Sayde, Joseph Tatham, Alan Lehotsky, Andrew Ladd, Mark Seneski, Aron Atkins
  • Publication number: 20040122644
    Abstract: System and methods high-performance simulation of the operation of a hardware device. A software object, based on a register transfer level description of the device written in a hardware description language, such as Verilog, is used for the simulation. The invention uses global analysis techniques (i.e., analysis of the design of the electronic device as a whole) to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).
    Type: Application
    Filed: November 7, 2003
    Publication date: June 24, 2004
    Inventors: William Neifert, Joshua Marantz, Richard Sayde, Joseph Tatham, Alan Lehotsky, Andrew Ladd, Mark Seneski, Aron Atkins
  • Publication number: 20040117167
    Abstract: System and methods for simulating a software object generated from a hardware description of an electronic device. The hardware description is a register transfer level description of the device written in a hardware description language, such as Verilog. The invention uses global analysis techniques (i.e., analysis of the design of the hardware device as a whole) to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).
    Type: Application
    Filed: November 7, 2003
    Publication date: June 17, 2004
    Inventors: William Neifert, Joshua Marantz, Richard Sayde, Joseph Tatham, Alan Lehotsky, Andrew Ladd, Mark Seneski, Aron Atkins
  • Publication number: 20040117168
    Abstract: System and methods for analyzing the design of the hardware device as a whole, rather than in fragments. This provides a basis for a high-performance simulation of the hardware device from a register transfer level description of the device written in a hardware description language, such as Verilog. The invention uses global analysis techniques to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).
    Type: Application
    Filed: November 7, 2003
    Publication date: June 17, 2004
    Inventors: William Neifert, Joshua Marantz, Richard Sayde, Joseph Tatham, Alan Lehotsky, Andrew Ladd, Mark Seneski, Aron Atkins