Patents by Inventor William O'Leary
William O'Leary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10878932Abstract: Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.Type: GrantFiled: November 8, 2019Date of Patent: December 29, 2020Assignee: Micron Technology, Inc.Inventors: Kallol Mazumder, William O'Leary
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Publication number: 20200073775Abstract: Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.Type: ApplicationFiled: November 8, 2019Publication date: March 5, 2020Applicant: Micron Technology, Inc.Inventors: Kallol Mazumder, William O'Leary
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Patent number: 10489260Abstract: Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.Type: GrantFiled: July 11, 2018Date of Patent: November 26, 2019Assignee: Micron Technology, Inc.Inventors: Kallol Mazumder, William O'Leary
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Publication number: 20180322937Abstract: Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.Type: ApplicationFiled: July 11, 2018Publication date: November 8, 2018Applicant: Micron Technology, Inc.Inventors: Kallol Mazumder, William O'Leary
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Patent number: 10043587Abstract: Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.Type: GrantFiled: July 20, 2016Date of Patent: August 7, 2018Assignee: Micron Technology, Inc.Inventors: Kallol Mazumder, William O'Leary
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Publication number: 20180025760Abstract: Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.Type: ApplicationFiled: July 20, 2016Publication date: January 25, 2018Applicant: Micron Technology, Inc.Inventors: Kallol Mazumder, William O'Leary
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Patent number: 6950957Abstract: Phase locked loops operable at low reference clock signal frequencies include a phase comparator having a phase detector, a digital counter, and a digital-to-analog converter. The phase detector provides an error signal indicative of a phase relationship between the reference clock signal and a feedback signal. The digital counter provides a count value indicative of the amount of phase error between the reference clock signal and the feedback signal. The digital-to-analog converter provides an error voltage signal proportional to the count value. Such phase comparators permit direct measurement of the amount of phase error prior to filtering and amplification by the phase locked loop. Direct measurement of the amount of phase error can be used to reduce the likelihood of saturating an amplifier of an active filter of the phase locked loop without the use of a pre-filter. Such phase locked loops are suitable for use in timing circuits of communications systems.Type: GrantFiled: September 11, 2000Date of Patent: September 27, 2005Assignee: ADC Telecommunications, Inc.Inventor: William O'Leary
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Patent number: 6664827Abstract: Phase locked loops adapted to filter and store data indicative of the control signal applied to an oscillator permit suppression of tracking in the event of a step change in the phase difference between the reference clock signal and the feedback signal in the phase locked loop. Such phase locked loops further facilitate compensation for drift of the oscillator. Such phase locked loops are suitable for use in timing circuits of communications systems.Type: GrantFiled: March 1, 2002Date of Patent: December 16, 2003Assignee: ADC Telecommunications, Inc.Inventors: William O'Leary, Edwin W. Rowand
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Publication number: 20020180498Abstract: Phase locked loops adapted to filter and store data indicative of the control signal applied to an oscillator permit suppression of tracking in the event of a step change in the phase difference between the reference clock signal and the feedback signal in the phase locked loop. Such phase locked loops further facilitate compensation for drift of the oscillator. Such phase locked loops are suitable for use in timing circuits of communications systems.Type: ApplicationFiled: March 1, 2002Publication date: December 5, 2002Inventors: William O'Leary, Edwin W. Rowand
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Patent number: 3985369Abstract: In an anti jack-knifing coupling arrangement between a tractor vehicle and a trailer wherein a turntable is mounted on the tractor vehicle for rotation about a vertical axis and carries a brake member for rotation therewith and having opposing horizontal parallel faces defining brake surfaces and brake callipers are mounted on the tractor vehicle for operative engagement with such brake surfaces, while themselves being restrained from movement about the vertical axis; the brake surfaces and the brake callipers are cooperatively disposed in a manner so as to be protected from exposure to rain and like elements and are kept clean and dry so that any possible slippage therebetween when the brake callipers are actuated to grip the brake surfaces is obviated.Type: GrantFiled: March 27, 1975Date of Patent: October 12, 1976Assignee: Artiloc U.S.A. Inc.Inventor: William O'Leary