Patents by Inventor William Orville Ramey
William Orville Ramey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8701091Abstract: A method and system for application development. Specifically, a generic console interface is provided that is capable of interacting with graphics applications. The console interface is capable of accessing a graphics application by detouring at least one predefined system call made by the graphics application. User input is intercepted that is related to the predefined system call that is detoured. The user input is communicated through the console interface. An operation is performed as implemented by the user input through a dynamically loadable module.Type: GrantFiled: December 15, 2005Date of Patent: April 15, 2014Assignee: Nvidia CorporationInventors: Matthias M. Wloka, Raul Aguaviva, Sebastien Julien Domine, Gregory E. James, William Orville Ramey, II
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Patent number: 8607151Abstract: A method of debugging an application operable on a graphics pipeline subunit. A plurality of draw call groups is accessed. Each draw call group comprises a respective plurality of draw calls, sharing common state attributes of a prescribed state. The plurality of selectable draw call groups is displayed. In response to a user selection, a plurality of selectable draw calls associated with the selected draw call group is displayed. A plurality of selectable graphics pipeline subunits is displayed. In response to a user selection of a selected subunit, a plurality of editable state information and graphical primitives associated with a selected draw call are displayed. The plurality of editable state information may be grouped such that a portion sharing common attributes of the prescribed state are in one group. In response to a user selection, changes may be made to the selected draw call or the selected draw call group.Type: GrantFiled: August 1, 2006Date of Patent: December 10, 2013Assignee: Nvidia CorporationInventors: Raul Aguaviva, Sebastien Julien Domine, William Orville Ramey, II
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Patent number: 8436870Abstract: A computer-implemented user interface and method for graphical processing analysis. More specifically, embodiments provide a convenient and effective mechanism for presenting GPU performance information such that one or more bottlenecking and/or underutilized graphics pipeline units may be identified. The presentation of the information enables quick comparison of all graphical operations within a frame for analysis with increased granularity. Additionally, the performance of graphical operations with common state attributes may be compared to more effectively and efficiently enhance GPU performance.Type: GrantFiled: August 1, 2006Date of Patent: May 7, 2013Assignee: Nvidia CorporationInventors: Raul Aguaviva, Jeffrey T. Kiel, Sebastien Julien Domine, William Orville Ramey, II
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Patent number: 8436864Abstract: A computer-implemented method and user interface for organizing graphical operations and displaying performance data of a graphics processing pipeline. More specifically, embodiments provide a convenient and effective mechanism for enhancing graphics processing by automatically determining and grouping graphical operations with similar state attributes relating to one or more units of the graphics pipeline. As such, pipeline adjustments for reducing execution time of one graphical operation may benefit other graphical operations with similar state attributes, thereby reducing the number of pipeline adjustments and allowing more careful selection of graphical operations to increase performance and reduce image degradation. Also, the display of the grouped graphical operations also provides information for determining the troublesome operations. In one embodiment, the groups are ranked by their respective execution time.Type: GrantFiled: August 1, 2006Date of Patent: May 7, 2013Assignee: Nvidia CorporationInventors: Raul Aguaviva, Jeffrey T. Kiel, Sebastien Julien Domine, William Orville Ramey, II
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Patent number: 8373717Abstract: The symmetrical properties of a group of vertices are leveraged to reconstruct the group using vertex data for a subset of the vertices and a set of control data. The subset of vertices is symmetrical to one or more other subsets of vertices in the group, and the control data includes information to reconstruct the one or more other subsets using the vertex data for the first set of vertices and symmetrical characteristics of the group. In some embodiments, reconstruction is performed using a geometry shader in a graphics processor to compute the additional vertices.Type: GrantFiled: April 25, 2007Date of Patent: February 12, 2013Assignee: NVIDIA CorporationInventors: William Orville Ramey, II, Henry Packard Moreton, Douglas H. Rogers
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Patent number: 7778800Abstract: A method of calculating utilization and bottleneck performance parameters of a processing unit within a graphical processing unit (GPU). The utilization is a measure of a percentage that the processing unit is utilized over a draw call execution time. The bottleneck is the sum of the time period that the processing unit is active, the time period that the processing unit is full and does not accept data from an upstream processing unit, minus the time period that the processing unit is paused because the downstream processing unit is busy and cannot accept data, all over the execution time of the draw call. Performance parameters may be determined by sampling the processing unit and incrementing a counter when a condition is true. The method is repeated for the same draw call, for each processing unit of the GPU, and for a plurality of draw calls comprising a frame.Type: GrantFiled: August 1, 2006Date of Patent: August 17, 2010Assignee: Nvidia CorporationInventors: Raul Aguaviva, Jeffrey T. Kiel, Sebastien Julien Domine, William Orville Ramey, II
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Publication number: 20080266286Abstract: A geometry shader of a graphics processor is configured to generate at least a portion of a particle system. The geometry shader receives vertex data including a reference set of vertices. The geometry shader also receives control data including information on how to create additional vertices for the particle system using the vertex data. The geometry shader processes the vertex data and control data to generate the additional vertices for the particle system. In some embodiments, the control data also includes information on other attributes of the generated vertices.Type: ApplicationFiled: April 25, 2007Publication date: October 30, 2008Applicant: NVIDIA CorporationInventors: William Orville Ramey, Henry Packard Moreton, Douglas H. Rogers
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Publication number: 20080266287Abstract: A geometry shader of a graphics processor decompresses a set of vertex data representing a simplified model to create a more detailed representation. The geometry shader receives vertex data including a number of vertices representative of a simplified model. The geometry shader decompresses the vertex data by computing additional vertices to create the more detailed representation. In some embodiments, the geometry shader also receives rules data including information on how the vertex data is to be decompressed.Type: ApplicationFiled: April 25, 2007Publication date: October 30, 2008Applicant: NVIDIA CorporationInventors: William Orville Ramey, Henry Packard Moreton, Douglas H. Rogers
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Publication number: 20080266296Abstract: The symmetrical properties of a group of vertices are leveraged to reconstruct the group using vertex data for a subset of the vertices and a set of control data. The subset of vertices is symmetrical to one or more other subsets of vertices in the group, and the control data includes information to reconstruct the one or more other subsets using the vertex data for the first set of vertices and symmetrical characteristics of the group. In some embodiments, reconstruction is performed using a geometry shader in a graphics processor to compute the additional vertices.Type: ApplicationFiled: April 25, 2007Publication date: October 30, 2008Applicant: NVIDIA CorporationInventors: William Orville Ramey, Henry Packard Moreton, Douglas H. Rogers
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Publication number: 20080034311Abstract: A method of debugging an application operable on a graphics pipeline subunit. A plurality of draw call groups is accessed. Each draw call group comprises a respective plurality of draw calls, sharing common state attributes of a prescribed state. The plurality of selectable draw call groups is displayed. In response to a user selection, a plurality of selectable draw calls associated with the selected draw call group is displayed. A plurality of selectable graphics pipeline subunits is displayed. In response to a user selection of a selected subunit, a plurality of editable state information and graphical primitives associated with a selected draw call are displayed. The plurality of editable state information may be grouped such that a portion sharing common attributes of the prescribed state are in one group. In response to a user selection, changes may be made to the selected draw call or the selected draw call group.Type: ApplicationFiled: August 1, 2006Publication date: February 7, 2008Inventors: Raul Aguaviva, Sebastien Julien Domine, William Orville Ramey
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Publication number: 20080033696Abstract: A method of calculating utilization and bottleneck performance parameters of a processing unit within a graphical processing unit (GPU). The utilization is a measure of a percentage that the processing unit is utilized over a draw call execution time. The bottleneck is the sum of the time period that the processing unit is active, the time period that the processing unit is full and does not accept data from an upstream processing unit, minus the time period that the processing unit is paused because the downstream processing unit is busy and cannot accept data, all over the execution time of the draw call. Performance parameters may be determined by sampling the processing unit and incrementing a counter when a condition is true. The method is repeated for the same draw call, for each processing unit of the GPU, and for a plurality of draw calls comprising a frame.Type: ApplicationFiled: August 1, 2006Publication date: February 7, 2008Inventors: Raul Aguaviva, Jeffrey T. Kiel, Sebastien Julien Domine, William Orville Ramey
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Publication number: 20080030511Abstract: A computer-implemented method and user interface for organizing graphical operations and displaying performance data of a graphics processing pipeline. More specifically, embodiments provide a convenient and effective mechanism for enhancing graphics processing by automatically determining and grouping graphical operations with similar state attributes relating to one or more units of the graphics pipeline. As such, pipeline adjustments for reducing execution time of one graphical operation may benefit other graphical operations with similar state attributes, thereby reducing the number of pipeline adjustments and allowing more careful selection of graphical operations to increase performance and reduce image degradation. Also, the display of the grouped graphical operations also provides information for determining the troublesome operations. In one embodiment, the groups are ranked by their respective execution time.Type: ApplicationFiled: August 1, 2006Publication date: February 7, 2008Inventors: Raul Aguaviva, Jeffrey T. Kiel, Sebastien Julien Domine, William Orville Ramey