Patents by Inventor William P Bischoff

William P Bischoff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6982521
    Abstract: A visual display has a cathode plate 101, having an emission layer 102 built up on a ceramic front layer. It has a thicker foundation layer 103. Vias from the front layer have their pitch fanned out to that of the cathode-plate back-layer vias 104. Other main components of the visual display are a frame 111, a back plate 112 and an anode 114 plate. The back plate and the frame are integrally formed of a number of layers of tape cast ceramic material. The back plate has a via and interconnect fan-out. The frame also has a via and interconnect arrangement for making electrical connection to the anode plate.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: January 3, 2006
    Inventors: Ingemar V Rodriguez, William P Bischoff
  • Publication number: 20020044130
    Abstract: A visual display has a cathode plate 101, having an emission layer 102 built up on a ceramic front layer. It has a thicker foundation layer 103. Vias from the front layer have their pitch fanned out to that of the cathode-plate back-layer vias 104.
    Type: Application
    Filed: June 1, 2001
    Publication date: April 18, 2002
    Applicant: Complete Substrate Solutions Limited
    Inventors: Ingemar V. Rodriguez, William P. Bischoff
  • Publication number: 20020017855
    Abstract: The front layer 1 shown in FIG. 1 is being tape cast in the direction of the arrow A from alumina ceramic material 2 onto a mylar layer 3. The doctor blade 4, which regulates the thickness T of the ceramic layer has serrations 5, which form parallel grooves 6 in the front surface 7 of the layer. After the material has set, by evaporation of the moisture allows the material to be sufficiently fluid for its casting, vias apertures 8 are punched in it, whilst it is still supported on the mylar, FIG. 2. They are filled with via material 9, FIG. 3, as described in more detail below. After via filling, the mylar layer is peeled from the tape cast ceramic.
    Type: Application
    Filed: June 1, 2001
    Publication date: February 14, 2002
    Applicant: Complete Substrate Solutions Limited
    Inventors: Anthony J. Cooper, Ingemar V. Rodriguez, William P. Bischoff, Abdullah Abel
  • Publication number: 20010048276
    Abstract: A display has a cathode 1 and an anode 2. These are in plate form and held spaced apart by a peripheral frame 3, to which they are both sealed. The cathode has an emission layer 11 deposited on a front ceramic layer 12 with vias 14 to the emission layer. The foundation layer is fired, ground flat and has via apertures cut through it and filled 17 prior to lamination of the front layer. Onto the back face of the substrate, preferably prior to deposition of the emission layer, is spun on a dielectric layer 21, which is developed with the aid of a temporary mask (not shown) to provide etchable tracks. These are etched to leave grooves 22 corresponding to metallic interconnections 23 from the foundation layer vias 17 to vias 24 in the next dielectric layer 25, typically thicker than the previous one 21. The metallic interconnections 23 are formed by screen printing and firing.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 6, 2001
    Applicant: Complete Substrate Solutions Limited
    Inventors: Ingemar V. Rodriguez, William P. Bischoff
  • Patent number: 5808856
    Abstract: A high energy multilayer ceramic capacitor formed of alternating ceramic and electrode layers, the capacitor being suitable for use in implantable medical devices. The ceramic layers are comprised of a dielectric composition of lead magnesium niobate with small amounts of dopants, namely, lithium niobate, copper oxide, magnesium titanate, manganese niobate, and zirconium oxide, with appropriate electrical terminations connected to the electrode layers. The capacitor thus fabricated exhibits greatly reduced ferroelectric effect, namely, less than 30% over a bias range of 0-1,000 volts. It has a breakdown voltage of at least 700 volts, a leakage current less than 10 pico amps at 1,000 volts, an energy density of greater than 10 J/cc, has a rectangular form factor 1.5 inches by 2.0 inches by 0.06 inch thick, and weighs no more than 30 grams.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: September 15, 1998
    Assignee: Microelectronic Packaging, Inc.
    Inventors: William P. Bischoff, Michael G. Bischoff
  • Patent number: 5680685
    Abstract: A method of fabricating a large, rectangular, multilayer ceramic capacitor formed of alternating ceramic and electrode layers. Capacitors so formed have a high dielectric constant, extremely low leakage current and an extremely low dissipation factor. Exemplary capacitors can be made with a lead magnesium niobate dielectric composition powder to which is added several organic constituents, including a surfactant and a plasticizer, plus small amounts of several dopants, such as lithium niobate, copper oxide, magnesium titanate, manganese niobate and zirconium oxide. That total mixture is ball milled to form a slip with very small grain size. The slip is cast as a thin tape on a Mylar backing, cut into a plurality of blanks, and alternating layers of the green tape ceramic and electrode layers are laminated on a polyvinyl alcohol coated foundation plate. Firing and sintering steps are followed by application of electrical terminations to complete the capacitor.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 28, 1997
    Assignee: Microelectronic Packaging, Inc.
    Inventor: William P. Bischoff
  • Patent number: 5603147
    Abstract: A high energy multilayer ceramic capacitor formed of alternating ceramic and electrode layers, the capacitor being suitable for use in implantable medical devices. The ceramic layers are comprised of a dielectric composition of lead magnesium niobate with small amounts of dopants, namely, lithium niobate, copper oxide, magnesium titanate, manganese niobate, and zirconium oxide, with appropriate electrical terminations connected to the electrode layers. The capacitor thus fabricated exhibits greatly reduced ferroelectric effect, namely, less than 30% over a bias range of 0-1,000 volts. It has a breakdown voltage of at least 700 volts, a leakage current less than 10 pico amps at 1,000 volts, an energy density of greater than 10 J/cc, has a rectangular form factor 1.5 inches by 2.0 inches by 0.06 inch thick, and weighs no more than 30 grams.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: February 18, 1997
    Assignee: Microelectronic Packaging, Inc.
    Inventors: William P. Bischoff, Michael G. Bischoff