Abstract: A semiconductor device which includes a substrate and a conductive pattern formed on the substrate. The conductive pattern includes at least two conductive lines adjacent one another. A low dielectric constant (LDC) material is dispersed between the at least two conductive lines. The LDC material includes a polymeric material including a polymer having a first and second end. The first end includes a functional group adapted to substantially bond to an insulating layer covering at least a portion of the substrate. The second end includes a functional group adapted to substantially bond to a dielectric material deposited over the LDC material. The polymeric material also includes air pockets therein which facilitate mitigation of capacitive crosstalk between the at least two conductive lines.

Abstract: An improved electrically erasable programmable read only memory (EEPROM) integrated circuit structure and method for its fabrication is disclosed, having an enhanced interface between the floating gate electrode and the underlying tunnel oxide. The structure is capable of a relatively higher floating gate breakdown voltage and is less subject to charge migration from the floating gate and resultant charge trapping in the tunnel oxide. The improvements comprise forming the floating gate electrode from amorphous silicon and doping the silicon floating gate by implantation with a dopant, such as arsenic or phosphorus, under conditions wherein the doping agent will not easily migrate into the underlying tunnel oxide layer.