Abstract: A time to digital converter with a successive approximation architecture (300) and a method thereof is provided. The time to digital converter (300) includes successive approximation analog to digital converter circuitry (310) configured for converting the differential voltage established in the digital to analog converter (305) of the successive approximation analog to digital converter circuitry (310) to a digital representation thereof, where the differential voltage corresponds to a measured time period representing a time difference between receipt of leading edges of two signals. Time to digital converter (300) may incorporate a current switching unit (340?) having a plurality of current switching circuits (303a-303n, 304a-304n) arranged in parallel to increase the precision of digital time output of time to digital converter (300). The plurality of current switching circuits (303a-303n, 304a-304n) can be selectively enabled to alter the sensitivity of the time to digital converter (300).

Abstract: A manually powered hand held electrical device such as a flashlight is provided. The device has an elongate housing, a power-requiring functional element, a hinge element at the back of the housing, and a crank arm having an end rotatably attached to the hinge. The hinge allows the crank arm to rotate within an arc of 270 degrees between a resting position and an operating position. The arc is within a plane that includes the longitudinal axis of the housing. In the resting position, the crank arm is parallel to the housing; in the operating position, it is orthogonal thereto. The hinge is rotatable about the longitudinal axis of the housing, and consequently so too is crank arm. The hinge is connectable to a generator; rotation of the hinge element powers the generator, and the generator provides power to the power-requiring functional element such as a light-emitting element.

Abstract: A manually powered hand held electrical device such as a flashlight is provided. The device has an elongate housing, a power-requiring functional element, a hinge element at the back of the housing, and a crank arm having an end rotatably attached to the hinge. The hinge allows the crank arm to rotate within an arc of 270 degrees between a resting position and an operating position. The arc is within a plane that includes the longitudinal axis of the housing. In the resting position, the crank arm is parallel to the housing; in the operating position, it is orthogonal thereto. The hinge is rotatable about the longitudinal axis of the housing, and consequently so too is crank arm. The hinge is connectable to a generator; rotation of the hinge element powers the generator, and the generator provides power to the power-requiring functional element such as a light-emitting element.

Abstract: A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Abstract: A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Abstract: A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Abstract: A clock signal can be synthesized by performing a clock and data recovery (CDR) operation on a potentially noisy clock source signal which has a known transition density. The CDR operation produces a desired clock signal in response to the clock source signal. In order to reduce crosstalk between plesiochronous receive and transmit clock domains of a serial data transceiver, a single common PLL is used both to recover the receive clock from the received data and to synthesize the transmit clock from a potentially noisy transmit clock source signal.

Abstract: The present invention provides a method and mechanism for regenerating the clock signal and recovering the data of a serial bit data stream. According to an embodiment, a circuit for recovering data from a serial bit stream may include a de-serializer configured for reclocking the serial bit stream using at least one reclocking signal, having a frequency with a phase, and de-serializing the serial bit stream into at least two bit streams. The circuit may further include a clock recovery loop filter having a second order filter coupled with the deserializer. The clock recovery loop filter may be configured for determining whether the de-serializer is reclocking the serial bit data stream at an optimum location and for generating at least one control signal to adjust the phase of the frequency of the at least one reclocking signal if the de-serializer is not reclocking the serial bit data stream at the optimum location.

Abstract: A control system and method for automatic control of an air vehicle during catapult launch includes a first pitch axis partition that includes an altitude hold control loop and a vertical rate control loop, and a second pitch axis partition that includes a constant throttle airspeed hold control loop. The control system also includes a vertical acceleration command select loop. The altitude hold control loop and the vertical rate control loop cooperatively determine a vertical rate loop vertical acceleration command. The constant throttle airspeed hold control loop determines a constant throttle airspeed hold vertical acceleration command. The vertical acceleration command select loop selects one of either the vertical rate loop vertical acceleration command or the constant throttle airspeed hold vertical acceleration command. A flight control system of the air vehicle drives the air vehicle to the selected vertical acceleration command.

Abstract: A circuit and method for driving the output signal, having a common-mode voltage and an output swing, of an integrated circuit. In accordance with an aspect of an embodiment of the present invention, a first power supply provides the termination voltage for the output signal and a second power supply provides the power to set the common mode voltage. In accordance with another aspect, the common-mode voltage and the output swing are programmable.

Abstract: A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.

Abstract: An analog to digital (A/D) converter apparatus is disclosed which increases spurious free dynamic range without adding a significant amount of noise. The apparatus includes a sample and hold circuit, a main range A/D converter for converting the sample and hold circuit output into a first digital signal, and a digital to analog (D/A) converter for converting the output of the main range A/D converter to an analog signal which is fed to a summing node. The output of the sample and hold circuit is also fed to the summing node through a first load resistor. The difference between the D/A output and the sample and hold output is generated at the summing node, and this difference is amplified and digitized by a subrange A/D converter. Added circuitry including a bootstrap amplifier and second load resistor are provided to increase the load impedance on the sample and hold output. An embodiment making use of multiple sample and hold circuits connected in parallel using a bootstrap amplifier is also disclosed.

Abstract: The present invention is a multimode sensor system that transmits power down a common bus coaxial cable typically using an alternating current power source. Each remote unit connected to the coaxial cable and through an isolation transformer converts the alternating current power to direct current power for an integrated circuit bus interface. The interface is connected to the sensors. The interface is externally pin programmable to provide a carrier at a frequency for a channel assigned to the remote unit. The carrier is provided by a ripple counter producing a frequency divided signal compared to a fixed reference frequency, where the result of the comparison controls a voltage controlled oscillator. When plural low frequency analog signals are to be transmitted over the common bus, an on-chip multiplexer multiplexes the signals to an off-chip, external analog-to-digital converter.

Abstract: A process for treating a sulfur-containing cell by employing an oxidant, such as a hypochlorite, in conjunction with an alkaline hydrolysis solution, such as a sodium hydroxide solution, to react with the sulfur-containing products to produce sulfides and sulfites and then have the oxidant convert the sulfides and sulfites to soluble sulfates followed by neutralization of the solution with a suitable acid, such as sulfuric acid, to produce a solution safe for conventional disposal.

Abstract: An analog-to-digital converter having error correction in the digital stages of the converter. A calibration microprocessor executes a correction value program prior to, or interspaced with, the normal operation of the converter. From either of two calibration programs, appropriate digital correction values are stored into a digital memory. The analog input signal is converted to a digital signal by a main range analog-to-digital converter, with the output of the converter addressing the memory containing the error correction values. The main range digital value is reconverted to an analog signal which is compared to the original input signal to determine the difference therebetween. This analog difference is converted to a digital signal and combined with the main range digital signal and the addressed correction values to produce the digital output signal of the conversion system.

Abstract: An analog to digital converter system is disclosed as comprising a conversion circuit operative for developing a digital output corresponding to the magnitude of an input analog signal, a calibration port arranged for receiving digital calibration data from an external source, adjustable calibration circuitry associated with the conversion circuit, and an adjustment mechanism for adjusting the calibration circuitry in response to data applied to the calibration port.

Abstract: A very high speed, high resolution analog to digital converter is detained including a subrange architecture, with the main range A/D including a digital to analog portion for producing an analog signal which can be summed with an amplified input analog signal. The summed analog signal is directed through a unity gain buffer to the subrange analog to digital converter, with the buffer isolating the high input capacitance of the subrange A/D from the summing node. The main range A/D provides a binary coded digital signal which approximates the input analog signal and which defines the most significant bits (MSB) of the digital output. The least significant bits (LSB) are had from the subrange A/D which provides at least one more bit than the number of MSB to provide overlap for forming the combined digital output signal.

Abstract: The present invention is a multimode sensor system that transmits power down a common bus coaxial cable typically using an alternating current power source. Each remote unit connected to the coaxial cable and through an isolation transformer converts the alternating current power to direct current power for an integrated circuit bus interface. The interface is connected to the sensors. The interface is externally pin programmable to provide a carrier at a frequency for a channel assigned to the remote unit. The carrier is provided by a ripple counter producing a frequency divided signal compared to a fixed reference frequency, where the result of the comparison controls a voltage controlled oscillator. When plural low frequency analog signals are to be transmitted over the common bus, an on-chip multiplexer multiplexes the signals to an off-chip, external analog-to-digital converter.

Abstract: An analog to digital converter (ADC) is presented which uses a calibration technique to reduce harmonic distortion in data acquisition systems. This mechanization also allows faster conversion rates than previously possible for high resolution analog-to-digital converters. This converter makes use of a subrange or "half Flash" architecture where the subrange digital-to-analog converter (DAC) is augmented with a software calibrated DAC which removes system nonlinearities. The advantage of this system is that it allows the building of higher speed data acquisition systems with higher spurious free dynamic range than would be possible with conventional techniques. By adding the correction to the input of the subrange ADC, correction resolution can be a fraction of a quanta. A second approach using the same mathematics places at the output of the ADC a RAM or ROM look up table which linearizes the transfer function.