Patents by Inventor William Planey

William Planey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flip-chip packaging
    Patent number: 7122885
    Abstract: A semiconductor die mounted between an X-lead frame and a support structure without bonding wires or straps. A power enhancement mode junction field effect transistor (JFET) die having a top surface defining a drain, and a bottom surface having a first metalized region defining a source and a second metalized region defining a gate, is positioned on a support structure. An X-lead frame is bonded to the support structure such that electrical contact is made with an external lead. Angular projections from the X-lead frame make contact with the top surface of the JFET, hold the die in place on the support structure, and form electrical continuity between the JFET drain and the external lead. A construction on the surface of the support structure is positioned directly under the source region on the bottom of the JFET die and forms electrical continuity between the JFET source and a second external lead.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: October 17, 2006
    Assignee: Lovoltech, Inc.
    Inventor: William Planey
  • Flip-chip packaging
    Publication number: 20040113247
    Abstract: A semiconductor die mounted between an X-lead frame and a support structure without bonding wires or straps. A power enhancement mode junction field effect transistor (JFET) die having a top surface defining a drain, and a bottom surface having a first metalized region defining a source and a second metalized region defining a gate, is positioned on a support structure. An X-lead frame is bonded to the support structure such that electrical contact is made with an external lead. Angular projections from the X-lead frame make contact with the top surface of the JFET, hold the die in place on the support structure, and form electrical continuity between the JFET drain and the external lead. A construction on the surface of the support structure is positioned directly under the source region on the bottom of the JFET die and forms electrical continuity between the JFET source and a second external lead.
    Type: Application
    Filed: December 5, 2003
    Publication date: June 17, 2004
    Applicant: LOVOL TECH, INC.
    Inventor: William Planey
  • Flip-chip packaging
    Patent number: 6747342
    Abstract: A semiconductor die mounted between an X-lead frame and a support structure without bonding wires or straps. A power enhancement mode junction field effect transistor (JFET) die having a top surface defining a drain, and a bottom surface having a first metalized region defining a source and a second metalized region defining a gate, is positioned on a support structure. An X-lead frame is bonded to the support structure such that electrical contact is made with an external lead. Angular projections from the X-lead frame make contact with the top surface of the JFET, hold the die in place on the support structure, and form electrical continuity between the JFET drain and the external lead. A construction on the surface of the support structure is positioned directly under the source region on the bottom of the JFET die and forms electrical continuity between the JFET source and a second external lead.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: June 8, 2004
    Assignee: Lovoltech, Inc.
    Inventor: William Planey