Abstract: A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the bottom surface to each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of the rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably be further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces.

Abstract: A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the surface of each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces.

Abstract: A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the bottom surface to each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of the rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably be further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces.

Abstract: A structure (10) is provided that is fabricated as a ball grid array substrate that includes a substrate dielectric (14), a power ring (18), a ground ring (20), a plurality of traces, and a second metal layer (16). The substrate dielectric (14) includes a first side, a second side, and a cavity formed therein. The power ring (18), the ground ring (20), and the plurality of traces are provided on the first side of the substrate dielectric (14). The plurality of traces, for example, may include a signal connection (22), a ground connection (24), and a power connection (26). The second metal layer (16) is provided on the second side of the substrate dielectric (14) and is electrically coupled to the first side. For example, the second metal layer (16) may serve as an active ground plane and electrically couple to a variety of ground connections, such as the ground connection (24), and the ground ring (20) through vias in the substrate dielectric (14).

Abstract: A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the bottom surface to each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of the rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably be further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces.

Abstract: A structure (10) is provided that is fabricated as a ball grid array substrate that includes a substrate dielectric (14), a power ring (18), a ground ring (20), a plurality of traces, and a second metal layer (16). The substrate dielectric (14) includes a first side, a second side, and a cavity formed therein. The power ring (18), the ground ring (20), and the plurality of traces are provided on the first side of the substrate dielectric (14). The plurality of traces, for example, may include a signal connection (22), a ground connection (24), and a power connection (26). The second metal layer (16) is provided on the second side of the substrate dielectric (14) and is electrically coupled to the first side. For example, the second metal layer (16) may serve as an active ground plane and electrically couple to a variety of ground connections, such as the ground connection (24), and the ground ring (20) through vias in the substrate dielectric (14).

Abstract: A semiconductor package includes a stiffener strip (10) having a die pad (18) and a body portion (12). A first surface (4) of the die pad (18) is offset from a second surface (3) of the body portion (12) a predetermined amount. The stiffener strip (10) includes an internal edge (27) concentrically disposed about the die pad (18) and tie straps (16) connecting the internal edge (27) to the die pad (18). A die (28) is affixed to the first surface (4) of the die pad (18). A substrate (20) has a first surface (17) and a second surface (19), with the second surface (19) being affixed to the first surface (2) of the body portion (12). The substrate (20) includes a window (22) and conductive elements (24). A plastic molding material (33) encompasses the die (28), at least a portion of the stiffener strip (10), and at least a portion of the substrate (20).

Abstract: A ball grid array package (62) having a deformable metal layer (20) is provided that includes a heat spreader (60), a stiffener (40) having a cavity and mounted to the heat spreader (60), a substrate (22), and a die (50). The substrate (22) includes a dielectric layer (10) with a cavity and cut-outs, the deformable metal layer (20), and a plurality of electrical traces for connection to solder balls. The dielectric layer (10) couples to the stiffener (40) through a second side and to the deformable metal layer (20) through the first side. The deformable metal layer (20) includes a cavity, a power ring (26), a ground ring (24), and a plurality of traces serving as either a ground connection, a signal connection, or a power connection for coupling with the plurality of solder balls.

Abstract: A light modulating device such as a liquid crystal display or polarizer is fabricated using optically biaxial plastic material as a substrate. The plastic biaxial material replaces the glass substrate of the LCD, or the cellulose acetate butyrate (CAB) of the polarizer. The biaxial material is a type of stretched plastic, which is more flexible than glass, and much thinner in typical display applications. Typical plastic biaxial materials are chemically stable with liquid crystals and much more stable than isotropic plastics (CAB). The material is optically anistropic, but optical axes of the material are chosen to be outside the field of view over which the device will be observed.

Abstract: Electronic circuitry for providing compensatory amplification to restore speech clarity for aurally handicapped persons comprising multiple active filters in a lowpass, bandpass, highpass (LP/BP/HP) configuration which provides composite filter responses applicable to infinite combinations of hearing deficiencies through multiple adjustments of filter gains, BP center frequency, LP/HP break frequencies, and BP filter "Q". This action achieves a precise corrective hearing response in wearable behind-the-ear and in-the-ear hearing aids.