Abstract: A computer system that employs Peripheral Component Interconnect Express (PCIe) links includes devices that generate a PCIe packet having a header portion that is smaller than the header portion for a conventional PCI packet. The devices may be an endpoint device, such as a graphics processor, and a chipset, such as a root-complex. The reduced size header improves the bus throughput efficiency of the computer system and reduces power requirements for the computer system.

Abstract: A method and system for supporting multiple display interface standards are disclosed. Specifically, one embodiment of the present invention sets forth a computing device, which includes a processing unit and a display interface. The display interface further includes a formatting logic and a set of output pins, wherein the formatting logic is configured to derive a first set of output signals conforming to a first display interface standard from a data stream, drive the first set of output signals via a set of output pins to a first display device supporting the first display interface standard, support a second display interface standard instead of the first display interface standard in response to a state change and derive the first set of output signals conforming to the second display interface standard, and drive the first set of output signals via the same set of output pins to a second display device supporting the second display interface standard.

Abstract: System and apparatus for capacitively coupling signals with an integrated circuit (IC) are described. Capacitive elements disposed with a transmitting IC effectively function as AC coupling capacitors for a PCIe, DisplayPort™ or other interconnect linking the transmitting IC with a receiver disposed remote there from. Integrating the coupling capacitors allows for a smaller and more economical design for the circuits that utilize the interconnect.

Abstract: The present invention pertains to a computer chassis with improved airflow to reduce the occurrence of trapped air pockets and increase heat transfer from components within the chassis. The computer chassis includes a plurality of chambers, wherein each of the chambers is separated by a partition. The partitions are operable to reduce the occurrence of trapped air pockets and increase heat transfer from components of the chassis by causing air to flow through each of the chambers. The computer chassis further includes at least two air vents, wherein each of the chambers is coupled to at least one of the at least two air vents through which air enters the chamber, and wherein each of the chambers is coupled to at least one of the at least two air vents through which air exits the chamber.

Abstract: System and apparatus for capacitively coupling signals with an integrated circuit (IC) are described. Capacitive elements disposed with a transmitting IC effectively function as AC coupling capacitors for a PCIe, DisplayPort™ or other interconnect linking the transmitting IC with a receiver disposed remote there from. Integrating the coupling capacitors allows for a smaller and more economical design for the circuits that utilize the interconnect.

Abstract: A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.

Abstract: In a computer system employing PCI Express (PCIe) links, the PCIe bandwidth is increased by configuring an endpoint device with at least two PCIe interfaces, and coupling the first of these interfaces with a PCIe interface of a system controller and the second of these PCIe interfaces with an expansion PCIe interface of an I/O controller. Therefore, the endpoint device's performance becomes more efficient. For example, if the endpoint device is a graphics processing unit, then the endpoint device can execute more frames per second. When a read request is split up and issued as multiple read requests over the at least two PCIe interfaces, the multiple read completion packets that are received in response thereto are ordered in accordance with the timing of the multiple read requests.

Abstract: Systems and apparatus for capacitively coupling signals with an integrated circuit (IC) are described. Capacitive elements disposed within a transmitting IC effectively function as AC coupling capacitors for a PCIe, DisplayPort™ or other interconnect linking the transmitting IC with a receiver disposed remote there from. Integrating the coupling capacitors allows for a smaller and more economical design for the circuits that utilize the interconnect.

Abstract: Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed to contiguous address ranges in the same target device. An opportunistic merging procedure is advantageously used that merges a first request with a later request if the first request and the later request are mergeable and are received within a holdoff period that is dynamically determined based on a level of bus activity; otherwise, requests can be transmitted without merging.

Abstract: A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.

Abstract: A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.