Patents by Inventor William R. Halleck
William R. Halleck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11899615Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.Type: GrantFiled: January 27, 2023Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z Chrysos, John R. Ayers, Dheeraj R. Subbareddy
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Publication number: 20230169032Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.Type: ApplicationFiled: January 27, 2023Publication date: June 1, 2023Inventors: NEVINE NASSIF, YEN-CHENG LIU, KRISHNAKANTH V. SISTLA, GERALD PASDAST, SIVA SOUMYA EACHEMPATI, TEJPAL SINGH, ANKUSH VARMA, MAHESH K. KUMASHIKAR, SRIKANTH NIMMAGADDA, CARLETON L. MOLNAR, VEDARAMAN GEETHA, JEFFREY D. CHAMBERLAIN, WILLIAM R. HALLECK, GEORGE Z. CHRYSOS, JOHN R. AYERS, DHEERAJ R. SUBBAREDDY
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Patent number: 11586579Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.Type: GrantFiled: October 28, 2021Date of Patent: February 21, 2023Assignee: Intel CorporationInventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z. Chrysos, John R. Ayers, Dheeraj R. Subbareddy
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Patent number: 11354264Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: GrantFiled: February 25, 2021Date of Patent: June 7, 2022Assignee: INTEL CORPORATIONInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Patent number: 11294852Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.Type: GrantFiled: June 30, 2020Date of Patent: April 5, 2022Assignee: Intel CorporationInventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z. Chrysos, John R. Ayers, Dheeraj R. Subbareddy
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Publication number: 20220050805Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.Type: ApplicationFiled: October 28, 2021Publication date: February 17, 2022Inventors: NEVINE NASSIF, YEN-CHENG LIU, KRISHNAKANTH V. SISTLA, GERALD PASDAST, SIVA SOUMYA EACHEMPATI, TEJPAL SINGH, ANKUSH VARMA, MAHESH K. KUMASHIKAR, SRIKANTH NIMMAGADDA, CARLETON L. MOLNAR, VEDARAMAN GEETHA, JEFFREY D. CHAMBERLAIN, WILLIAM R. HALLECK, GEORGE Z. CHRYSOS, JOHN R. AYERS, DHEERAJ R. SUBBAREDDY
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Publication number: 20210182231Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: ApplicationFiled: February 25, 2021Publication date: June 17, 2021Inventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Patent number: 10963415Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: GrantFiled: February 26, 2020Date of Patent: March 30, 2021Assignee: INTEL CORPORATIONInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Patent number: 10931329Abstract: An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.Type: GrantFiled: December 29, 2016Date of Patent: February 23, 2021Assignee: Intel CorporationInventors: Rahul R. Shah, William R. Halleck, Fulvio Spagna, Venkatraman Iyer
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Publication number: 20200334196Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.Type: ApplicationFiled: June 30, 2020Publication date: October 22, 2020Inventors: NEVINE NASSIF, YEN-CHENG LIU, KRISHNAKANTH V. SISTLA, GERALD PASDAST, SIVA SOUMYA EACHEMPATI, TEJPAL SINGH, ANKUSH VARMA, MAHESH K. KUMASHIKAR, SRIKANTH NIMMAGADDA, CARLETON L. MOLNAR, VEDARAMAN GEETHA, JEFFREY D. CHAMBERLAIN, WILLIAM R. HALLECK, GEORGE Z. CHRYSOS, JOHN R. AYERS, DHEERAJ R. SUBBAREDDY
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Patent number: 10795853Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.Type: GrantFiled: September 30, 2017Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z. Chrysos, John R. Ayers, Dheeraj R. Subbareddy
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Publication number: 20200293480Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: ApplicationFiled: February 26, 2020Publication date: September 17, 2020Applicant: INTEL CORPORATIONInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Patent number: 10599602Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: GrantFiled: June 20, 2019Date of Patent: March 24, 2020Assignee: Intel CorporationInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Publication number: 20190310959Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: ApplicationFiled: June 20, 2019Publication date: October 10, 2019Applicant: INTEL CORPORATIONInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Patent number: 10372657Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The low pin count PIPE interface is configured to transfer register commands between the PHY and MAC blocks over the small set of wires in a time-multiplexed manner to support read and write access of the PHY and MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture when operating in a PIPE mode and a serialization and deserialization (SERDES) architecture when operating in a SERDES mode.Type: GrantFiled: December 26, 2016Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Patent number: 10324882Abstract: An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.Type: GrantFiled: December 29, 2016Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: William R. Halleck, Rahul R. Shah, Venkatraman Iyer
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Patent number: 10152446Abstract: An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.Type: GrantFiled: October 1, 2016Date of Patent: December 11, 2018Assignee: Intel CorporationInventors: Venkatraman Iyer, Mahesh Wagh, William R. Halleck, Rahul R. Shah
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Patent number: 10025746Abstract: A signal is received, a boundary of which is to be sent in alignment with a sync counter value. A nominal latency of a link is determined based on the sync counter value. Additional latency is applied to the signal to increase the nominal latency to a target latency for the link.Type: GrantFiled: December 20, 2014Date of Patent: July 17, 2018Assignee: Intel CorporationInventors: William R. Halleck, Rahul Shah, Venkatraman Iyer
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Publication number: 20180191523Abstract: An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Inventors: Rahul R. Shah, William R. Halleck, Fulvio Spagna, Venkatraman Iyer
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Publication number: 20180181525Abstract: Systems, methods, and apparatuses involve a PHY coupled to a MAC. The PHY can include a drift buffer coupled to an output of a receiver and a bypass branch coupled to the output of the receiver. The PHY includes a clocking multiplexer that includes a first clock input coupled to a recovered clock of the PHY and a second clock input coupled to a p-clock of the MAC; and a clock output configured to output one of the recovered clock or the p-clock based on a selection input value. The PHY includes a bypass multiplexer that includes a first data input coupled to an output of a drift buffer and a second data input coupled to the bypass branch; and a data output configured to output one of the output of the drift buffer or data from the bypass branch based on the section input value of the clocking multiplexer.Type: ApplicationFiled: December 26, 2016Publication date: June 28, 2018Inventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee