Patents by Inventor William R. Kelly
William R. Kelly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11958882Abstract: Disclosed herein are methods of preparing a composition comprising crystalline biomolecules, for example, crystalline antibodies. In exemplary embodiments, the method comprises forming a fluidized bed of crystalline biomolecules using, for example, a counter-flow centrifuge to exchange buffer and/or to concentrate the crystalline biomolecules in a solution. Also provided are methods of detecting crystalline biomolecules and/or amorphous biomolecules in a sample.Type: GrantFiled: March 14, 2018Date of Patent: April 16, 2024Assignee: AMGEN INC.Inventors: Rizwan Sharnez, William Trieu, Marc A. Caporini, Ron C. Kelly, Neill Burt, Laura Nicholson, Twinkle R. Christian
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Patent number: 11374732Abstract: Embodiments of the present disclosure provide an apparatus including: a phase detector for detecting a write frequency of a deserializer and a read frequency of a serializer, such that the phase detector outputs a first code sequence in response to the write frequency being greater than the read frequency, or a second code sequence at the rotator input in response to the write frequency being less than the read frequency; and a phase rotator for receiving the first code sequence or the second code sequence from the phase rotator to transmit a pacing signal having the read frequency to the deserializer, wherein the pacing signal causes the read frequency to increase or decrease based on whether the read frequency is different from the write frequency.Type: GrantFiled: December 24, 2019Date of Patent: June 28, 2022Assignee: Marvell Asia Pte, Ltd.Inventors: Michael A. Sorna, William R. Kelly, Louis T. Fasano
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Publication number: 20220006462Abstract: Embodiments of the present disclosure provide an apparatus including: a phase detector for detecting a write frequency of a deserializer and a read frequency of a serializer, such that the phase detector outputs a first code sequence in response to the write frequency being greater than the read frequency, or a second code sequence at the rotator input in response to the write frequency being less than the read frequency; and a phase rotator for receiving the first code sequence or the second code sequence from the phase rotator to transmit a pacing signal having the read frequency to the deserializer, wherein the pacing signal causes the read frequency to increase or decrease based on whether the read frequency is different from the write frequency.Type: ApplicationFiled: December 24, 2019Publication date: January 6, 2022Inventors: Michael A. Sorna, William R. Kelly, Louis T. Fasano
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Patent number: 9235543Abstract: A system for detecting one or more signals at a PCI Express interface includes a receiver configured to receive a signal at the PCI Express interface, and a peak detector configured to detect one or more signals based on level sensing, and identify one or more data sampling points to set an amplitude threshold. A comparator is configured to compare an amplitude of the received signal with the amplitude threshold, and a processor is configured to confirm that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The processor is also configured to disable a signal detector that can detect one or more low frequency signals. The system also includes a tester configured to test whether the detected signal is correct.Type: GrantFiled: November 26, 2012Date of Patent: January 12, 2016Assignee: International Business Machines CorporationInventors: Hayden C Cranford, Jr., Daniel M Dreps, William R Kelly
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Patent number: 9213667Abstract: Methods for detecting one or more signals at a PCI Express interface includes receiving, a signal by a receiver at the PCI Express interface. The methods further include identifying one or more data sampling points to set an amplitude threshold. Further, the method includes comparing an amplitude of the received signal with the amplitude threshold. The method also includes confirming that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The method also includes disabling a signal detector of the PCI Express interface to save power. The signal detector is configured to detect one or more low frequency signals; and testing whether the detected signal is correct.Type: GrantFiled: February 28, 2013Date of Patent: December 15, 2015Assignee: International Business Machines CorporationInventors: Hayden C Cranford, Jr., Daniel M Dreps, William R Kelly
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Patent number: 9209948Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.Type: GrantFiled: January 19, 2015Date of Patent: December 8, 2015Assignee: International Business Machines CorporationInventors: Eugene R. Atwood, Matthew B. Baecher, Minhan Chen, Hayden C. Cranford, Jr., William R. Kelly, Todd M. Rasmus
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Publication number: 20150145710Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.Type: ApplicationFiled: November 26, 2013Publication date: May 28, 2015Applicant: International Business Machines CorporationInventors: EUGENE R. ATWOOD, MATTHEW B. BAECHER, WILLIAM R. KELLY, JOSEPH F. LOGAN, PINPING SUN
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Patent number: 9041572Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.Type: GrantFiled: November 26, 2013Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Eugene R. Atwood, Matthew B. Baecher, William R. Kelly, Joseph F. Logan, Pinping Sun
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Publication number: 20150131707Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.Type: ApplicationFiled: January 19, 2015Publication date: May 14, 2015Inventors: EUGENE R. ATWOOD, MATTHEW B. BAECHER, MINHAN CHEN, HAYDEN C. CRANFORD, JR., WILLIAM R. KELLY, TODD M. RASMUS
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Patent number: 9014254Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.Type: GrantFiled: June 19, 2013Date of Patent: April 21, 2015Assignee: International Business Machines CorporationInventors: Eugene R. Atwood, Matthew B. Baecher, Minhan Chen, Hayden C. Cranford, Jr., William R. Kelly, Todd M. Rasmus
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Publication number: 20140376603Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.Type: ApplicationFiled: June 19, 2013Publication date: December 25, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: EUGENE R. ATWOOD, MATTHEW B. BAECHER, MINHAN CHEN, HAYDEN C. CRANFORD, Jr., WILLIAM R. KELLY, TODD M. RASMUS
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Patent number: 8767531Abstract: A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.Type: GrantFiled: June 14, 2011Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Frank D. Ferraiolo, William R. Kelly, Robert J. Reese, Susan M. Rubow, Michael B. Spear
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Publication number: 20140149629Abstract: Methods for detecting one or more signals at a PCI Express interface includes receiving, a signal by a receiver at the PCI Express interface. The methods further include identifying one or more data sampling points to set an amplitude threshold. Further, the method includes comparing an amplitude of the received signal with the amplitude threshold. The method also includes confirming that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The method also includes disabling a signal detector of the PCI Express interface to save power. The signal detector is configured to detect one or more low frequency signals; and testing whether the detected signal is correct.Type: ApplicationFiled: February 28, 2013Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hayden C. Cranford, JR., Daniel M. Dreps, William R. Kelly
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Publication number: 20140149627Abstract: A system for detecting one or more signals at a PCI Express interface includes a receiver configured to receive a signal at the PCI Express interface, and a peak detector configured to detect one or more signals based on level sensing, and identify one or more data sampling points to set an amplitude threshold. A comparator is configured to compare an amplitude of the received signal with the amplitude threshold, and a processor is configured to confirm that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The processor is also configured to disable a signal detector that can detect one or more low frequency signals. The system also includes a tester configured to test whether the detected signal is correct.Type: ApplicationFiled: November 26, 2012Publication date: May 29, 2014Applicant: International Business Machines CorporationInventors: Hayden C. Cranford, JR., Daniel M. Dreps, William R. Kelly
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Patent number: 8401135Abstract: A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.Type: GrantFiled: February 2, 2010Date of Patent: March 19, 2013Assignee: International Business Machines CorporationInventors: Troy J. Beukema, William R. Kelly, Michael A. Sorna, Daniel W. Storaska
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Publication number: 20120151247Abstract: A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.Type: ApplicationFiled: June 14, 2011Publication date: June 14, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Frank D. Ferraiolo, William R. Kelly, Robert J. Reese, Susan M. Rubow, Michael B. Spear
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Patent number: 8139700Abstract: A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.Type: GrantFiled: June 26, 2009Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Troy J. Beukema, Steven M. Clements, Chun-Ming Hsu, William R. Kelly, Elizabeth M. May, Sergey V. Rylov
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Publication number: 20110188566Abstract: A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.Type: ApplicationFiled: February 2, 2010Publication date: August 4, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Troy J. Beukema, William R. Kelly, Michael A. Sorna, Daniel W. Storaska
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Patent number: 7869544Abstract: An eyewidth of a data signal is determined by steps including: (a) recovering a phase of a clock from a data signal as a sampling clock; (b) shifting the phase of the sampling clock away from the first phase by a count multiplied by predetermined phase amount; (c) sampling the data signal with the shifted sampling clock phase to obtain sample data; d) determining whether the sample data contains error; (e) when the sample data does not contain error, recovering the phase of the clock from the data signal again for use as the first phase of the sampling clock, increasing the count value and repeating steps (b) through (e); and f) when the sample data contains error, determining the eyewidth based on the last shifted phase of the sampling clock prior to determining that the sample data contains error.Type: GrantFiled: January 3, 2008Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Michael A. Sorna, William R. Kelly, Daniel W. Storaska
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Publication number: 20100329403Abstract: A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.Type: ApplicationFiled: June 26, 2009Publication date: December 30, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Troy J. Beukema, Steven M. Clements, Chun-Ming Hsu, William R. Kelly, Elizabeth M. May, Sergey V. Rylov