Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.

Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.

Abstract: A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for restructuring an image processing pipeline. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; or splitting the directed acyclic graph into smaller graphs.

Abstract: A method is described. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes any of: recognizing there are a different number of kernels in the program code than stencil processors in the image processor; recognizing that at least one of the kernels is more computationally intensive than another one of the kernels; and, recognizing that the program code has resource requirements that exceed the image processor's memory capacity.

Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors.

Abstract: According to some embodiments, systems, methods, apparatus, computer program code and means are provided to interpolate from a first portion of a digital object having a first level of detail to a second portion of the digital object having a second level of detail, create a third portion of the digital object having a third level of detail based on the interpolating, and intersect a ray at the third portion.

Abstract: A system and method provide for determining in a computer system the intersections between a plurality of rays residing in three dimensional (3D) space and one or more surface elements residing in the 3D space. The rays or lines corresponding to the rays share a common intersection point. The method includes for each of the rays, storing the intersection point of the ray with a projection surface in the 3D space in a data structure in the computer system. For each of the surface elements, determining using projection a two-dimensional (2D) region representing the projection of the surface element onto the projection surface; and determining using intersection testing which points stored in the data structure are inside the 2D region. The points determined to be inside the 2D region represent intersection points between the surface element and the rays corresponding to the points.

Abstract: A graphics processing subsystem is programmed with shader programs that make calls to an abstract interface. One or more subshaders implementing the functions of the abstract interface can also be defined. The binding of interfaces to functions is resolved by a language runtime module that compiles the subshaders. As shader programs are compiled, the runtime module determines whether each method call is associated with an interface function. For each interface method call, the runtime module determines the appropriate implementation of the interface to be bound to the method call. Once the appropriate implementation is identified, the interface binding is created using string substitution or indirect addressing instructions. At the time of compilation, which may be during the execution of the rendering application, the desired combinations of subshaders are specified and compiled into a combined shader program, which can then be executed by the graphics processing subsystem.

Abstract: According to some embodiments, systems, methods, apparatus, computer program code and means are provided to interpolate from a first portion of a digital object having a first level of detail to a second portion of the digital object having a second level of detail, create a third portion of the digital object having a third level of detail based on the interpolating, and intersect a ray at the third portion.

Abstract: A system and method for interfacing graphics program modules written to execute on a plurality of functional units of a graphics processor using a shared memory. A central processing unit (CPU) receives a first graphics program module that outputs a first parameter referenced by a first graphics program module identifier, a second graphics program module that inputs the first parameter by referencing the first graphics program module identifier, and a first data structure that includes, in a pre-defined order, a list of first data structure identifiers. The CPU identifies a memory location in the shared memory, based on the pre-defined order of the first data structure identifiers, for one of the first data structure identifiers that is the same as the first graphics program module identifier. The CPU modifies the first and second graphics program modules to reference the first parameter by the identified memory location in the shared memory.

Abstract: An instrument includes a probe providing a single signal path for conveying a signal from a circuit under test to the instrument. A receiver circuit within the instrument divides the path into an analog path and a digital path. The digital path includes a comparator for determining the logic state of the signal and producing a digital representation of the signal under test. The analog path includes a multiplexer to selectively couple one of a plurality of analog input signals to an output terminal for viewing on an oscilloscope. Preferably, the probe head includes a buffer amplifier to reduce loading on the circuit under test and to increase bandwidth of the signals conveyed along the test cable to the instrument. An electrically trimmable resistor is employed to terminate the transmission line of the test cable in its characteristic impedance in order to reduce reflections and maintain transmission bandwidth.

Abstract: A multi-channel, low input capacitance signal probe head has a housing that receives one or more substrates having input signal pads exposed on one end of the substrate. The substrate is positioned in the housing such that the signal contact pads are exposed at an open end of the housing. A removable signal contact holder mounts to the housing and supporting electrically conductive elastomer signal contacts. The holder is disposed over an open end of housing such that the elastomer signal contacts engage the input signal pads. A probe head retention member is provided for securing the multi-channel signal probe head to a device under test.

Abstract: An instrument includes a probe providing a single signal path for conveying a signal from a circuit under test to the instrument. A receiver circuit within the instrument divides the path into an analog path and a digital path. The digital path includes a comparator for determining the logic state of the signal and producing a digital representation of the signal under test. The analog path includes a multiplexer to selectively couple one of a plurality of analog input signals to an output terminal for viewing on an oscilloscope. Preferably, the probe head includes a buffer amplifier to reduce loading on the circuit under test and to increase bandwidth of the signals conveyed along the test cable to the instrument. An electrically trimmable resistor is employed to terminate the transmission line of the test cable in its characteristic impedance in order to reduce reflections and maintain transmission bandwidth.

Abstract: A multi-channel, low input capacitance signal probe head has a housing that receives one or more substrates having input signal pads exposed on one end of the substrate. The substrate is positioned in the housing such that the signal contact pads are exposed at an open end of the housing. A removable signal contact holder mounts to the housing and supporting electrically conductive elastomer signal contacts. The holder is disposed over an open end of housing such that the elastomer signal contacts engage the input signal pads. A probe head retention member is provided for securing the multi-channel signal probe head to a device under test.

Abstract: A latching electrical connector with a body connectable to a receptacle and having a latch mechanism that mechanically engages the receptacle to resist disconnection. A flexible electrical cable extends from the body, and a grip element is connected to the latch mechanism to unlatch the mechanism upon pulling. The grip element is flexibly connected to the latch mechanism so that it may be folded aside to provide a compact arrangement.