Abstract: A silicon wafer 2 has an ultra thin central portion 2 that is supported by a circumferential rim 3 of thicker silicon. The central region is thinned by conventional means using conventional removal apparatus. As an alternative method, the central portion is removed using a photoresist mask or a combination of a photoresist mask and a hard mask.

Abstract: The current gain, beta, of a vertical transistor having an emitter formed in an epitaxial base on a substrate collector is reduced by forming a high impurity region of the conductivity type of the base at the base-collector boundary to increase the base width greater than the vertical distance between the emitter and collector. A plurality of vertical transistors having identical emitters and a common collector may be simultaneously fabricated with different current gains by individually selecting the horizontal dimensions of the buried high impurity regions.

Abstract: An amorphous semiconductor device on a silicon substrate having a first level contact and interconnect of aluminum and coextensive layer of molybdenum and a second level contact and interconnect of molybdenum and coextensive layer of aluminum. Contacts to the amorphous device are by the two molybdenum layers and the contact of the second level contacts to the substrate is through the first level contacts.

Abstract: A silicon substrate integrated circuit having a layer of aluminum forming Schottky contacts with lightly doped N conductivity regions and silicon doped aluminum forming ohmic contacts to heavily doped N conductivity regions and forming interconnects between contacts.

Abstract: A bipolar transistor process and device wherein the transistor is fabricated within a laterally isolated device region, into which is formed a lateral intradevice isolation groove prior to formation of device/active and contact regions. The lateral intradevice isolation groove with the lateral device isolation assists in self-alignment of device regions. The lateral intradevice isolation permits the simultaneous formation through a single mask of an active region and a contact region for a different active region both on the same planar surface of a semiconductor substrate and facilitates extremely close spacing of active regions at the planar surface.

Abstract: A metallic ground grid is fabricated by forming a conductor on the isolation barrier of an integrated circuit through openings in a first insulated layer to a depth less than the first insulated layer, forming a second insulated layer on said first conductor to the height of the first insulated layer, and interconnecting selected areas of the integrated circuit and the first conductor through openings in the insulated layers by a second conductor.

Abstract: In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lightly doped substrate base and heavily doped emitter and collector. The lateral transistor's collector isolates the lateral transistor's base from the vertical transistor's collector.This integrated circuit approach includes the I.sup.2 L structure of the present invention and T.sup.2 L devices. The I.sup.2 L transistors are in dielectrically isolated regions with the vertical transistors emitter being connected to the polycrystalline support through a vertical opening in the dielectric isolation.

Abstract: PROM wafers having fuses on raised oxide are reworked by stripping the fuses and connectors, non-selectively etching the oxide layer to form a substantially planar, oxide surface resulting from the differential etching rate of the heavily phosphorus doped raised oxide surface compared to the remainder of lightly doped oxide, increasing the oxide layer thickness and forming new fuses and connectors on the new oxide.

Abstract: In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lightly doped substrate base and heavily doped emitter and collector. The lateral transistor's collector isolates the lateral transistor's base from the vertical transistor's collector.This integrated circuit approach includes the I.sup.2 L structure of the present invention and T.sup.2 L devices. The I.sup.2 L transistors are in dielectrically isolated regions with the vertical transistors emitter being connected to the polycrystalline support through a vertical opening in the dielectric isolation.

Abstract: A method of forming fuses and two level interconnects including applying a layer of fusible material on an insulating layer and through contact apertures, cleaning said fusible layer by sputter etching, applying a layer of metallic material by sputtering, selectively patterning the metallic layer to form a top layer of contacts and interconnects and selectively patterning the fusible layer to form fusible elements and to form a bottom layer of contacts and interconnects.

Abstract: A metallic ground grid is fabricated by forming a conductor on the isolation barrier of an integrated circuit through openings in a first insulated layer to a depth less than the first insulated layer, forming a second insulated layer on said first conductor to the height of the first insulated layer, and interconnecting selected areas of the integrated circuit and the first conductor through openings in the insulated layers by a second conductor.

Abstract: Isolation of device locations in a monolithic semiconductor integrated circuit is provided by depositing a thin film effective as a polishing stop on a planar surface of the semiconductor body in which the devices are to be fabricated, etching isolation grooves into the body through the thin film, coating the surfaces of the grooves and the film with an insulator layer, and growing polycrystalline material over the insulator layer to fill the grooves. The polycrystalline material in excess of that required to fill the grooves, and any insulator layer covering the planar surface of the thin film, are polished away without affecting the underlying planar surface of the semiconductor body, because the thin film is adapted to withstand polishing without damage. Finally, the thin film is stripped away leaving semiconductor islands having a planar surface and isolated by insulator layer-polycrystalline material filled moats. Devices are fabricated in these islands.

Abstract: A metallic ground conductor grid applied over a planar isolation barrier in an integrated circuit provides a low resistance ground. An insulating layer, formed over the ground conductor, has apertures therein for interconnecting selected areas of the integrated circuit to the ground conductor grid.