Patents by Inventor William R. Newberry

William R. Newberry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8866256
    Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a first conductive fuse bus having a triangular-shaped portion with a bottom surface aligned along a plane substantially parallel to a surface of the semiconductor substrate. The apparatus can include a second conductive fuse bus having a bottom surface aligned along the plane, and a plurality of fuse links coupled between the triangular-shaped portion of the first conductive fuse bus and the second conductive fuse bus.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 21, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: William R. Newberry
  • Publication number: 20140061852
    Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a first conductive fuse bus having a triangular-shaped portion with a bottom surface aligned along a plane substantially parallel to a surface of the semiconductor substrate. The apparatus can include a second conductive fuse bus having a bottom surface aligned along the plane, and a plurality of fuse links coupled between the triangular-shaped portion of the first conductive fuse bus and the second conductive fuse bus.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Inventor: William R. Newberry
  • Patent number: 5528157
    Abstract: A method for and a disassemblable prepackage arrangement for testing and burning-in an integrated circuit die which will be hermetically sealed within and form part of an overall integrated circuit package is herein disclosed. The die has a top and bottom surface and includes a plurality of die input/output terminals. The prepackage comprises a substrate including a top surface. The bottom of the die is disengagably attached to the top surface of the substrate. A lid is disengagably attached to the substrate in a way which hermetically seals the die within a space substantially defined by the substrate and the lid. Thereafter, the die input/output terminals are electrically connecting to external testing equipment for testing and burning-in the die while the die is in a hermetically sealed environment.
    Type: Grant
    Filed: November 15, 1994
    Date of Patent: June 18, 1996
    Assignee: National Semiconductor Corporation
    Inventors: William R. Newberry, Mark A. McClintick, Eric Falconer, William B. Aronson, Mark Lippold, David W. Joy