Abstract: Embodiments herein relate to a medical device for treating a cancerous tumor, the medical device having a first lead including a first wire and second wire; a second lead can include a third wire and fourth wire; and a first electrode in electrical communication with the first wire, a second electrode in electrical communication with the second wire, a third electrode in electrical communication with the third wire, and a fourth electrode in electrical communication with the fourth wire. The first and third electrodes form a supply electrode pair configured to deliver one or more electric fields to the cancerous tumor. The second and fourth electrodes form a sensing electrode pair configured to measure an impedance of the cancerous tumor independent of an impedance of the first electrode, the first wire, the third electrode, the third wire, and components in electrical communication therewith. Other embodiments are also included herein.

Abstract: A system and method for processing digital images that efficiently buffers pixel data relating to digital images is disclosed. Pixel values are read from an image storage memory and temporarily stored in a buffer memory according to a non-raster pattern. The processing of pixels also occurs according to a more efficient non-raster patter.

Abstract: In one example, a direct memory access controller includes a memory interface, a requestor interface, and an address generator. The memory interface is configured to cause a memory to provide at least a subset of data stored in the memory. The requestor interface is configured to receive a request for a consecutively addressed subset of the data stored in the memory to be provided in a non-consecutive order. The address generator is in communication with the requestor interface and the memory interface. The address generator is configured to, based on the request, sequentially generate non-consecutive addresses of the requested subset of the data to cause the memory to provide the requested subset of data in the requested non-consecutive order.

Abstract: A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers.

Abstract: A structure for a vehicle may include first and second spaced-apart members, first and second internally-threaded members, a module, first and second connecting members, and first and second fasteners. The first and second internally-threaded members may be connected to the first and second members, respectively. The module is positioned between the first and second members for a predetermined alignment relative thereto. The first and second connecting members include an outer surface having external threads and an inner surface having internal threads. The outer surface may engage a corresponding one of the internally-threaded members. The external and internal threads have opposite thread-handedness. The first and second fasteners engage the internal threads of the first and second connecting members, respectively. The first and second fasteners may move the first and second connecting members toward the module to clamp the module relative to the first and second members and maintain alignment therebetween.

Abstract: A system and method for processing digital images that efficiently buffers pixel data relating to digital images is disclosed. Pixel values are read from an image storage memory and temporarily stored in a buffer memory according to a non-raster pattern. The processing of pixels also occurs according to a more efficient non-raster pattern.

Abstract: A method of controlling the deposition and packing of refuse in a refuse vehicle body that includes a container handling lift and dump mechanism that automatically grasps, lifts and dumps refuse containers into a charging hopper and a packer panel and attached follower panel operable in the charging hopper, the method comprising causing the container handling lift and dump mechanism to pause before dumping a container in a lift and dump cycle until the packer panel is fully retracted.

Abstract: A structure for a vehicle may include first and second spaced-apart members, first and second internally-threaded members, a module, first and second connecting members, and first and second fasteners. The first and second internally-threaded members may be connected to the first and second members, respectively. The module is positioned between the first and second members for a predetermined alignment relative thereto. The first and second connecting members include an outer surface having external threads and an inner surface having internal threads. The outer surface may engage a corresponding one of the internally-threaded members. The external and internal threads have opposite thread-handedness. The first and second fasteners engage the internal threads of the first and second connecting members, respectively. The first and second fasteners may move the first and second connecting members toward the module to clamp the module relative to the first and second members and maintain alignment therebetween.

Abstract: The disclosed embodiments relate to a memory controller for retrieving a plurality of data stored in a memory in communication with the memory controller, the plurality of data being characterized by a first arrangement of first and second non-parallel arrays, such as one-dimensional arrays. The first array comprises at least first and second data of the plurality of data and the second array comprises at least the first data and third data of the plurality of data. The memory is operative to provide the at least first and second data of the first array before providing at least the third data of the second array when the memory is accessed based on an address of the first data in the memory and an amount of the plurality of data to provide starting from the address of the first data.

Abstract: A direct memory access controller comprises a plurality of registers defining parameters for multiple direct memory access transactions and transfer control circuitry responsive to data in the plurality of registers. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the parameters of the plurality of registers. At least two consecutive data transactions are executed with respect to non-contiguous system locations.

Abstract: A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers.

Abstract: A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers.

Abstract: An application specific integrated circuit (ASIC) comprises a first bus that communicates with inputs and outputs of N processing modules, where N is an integer greater than 1. A control module communicates with the first bus and a second bus that is different than the first bus, and that generates first control signals. A routing module communicates with the first bus, receives data via the second bus from a first memory, selectively routes the data to a first of the inputs, and selectively routes one of the outputs to a second of the inputs. The routing module selects the first and second of the inputs based on the first control signals.

Abstract: A direct memory access controller comprises a plurality of registers defining parameters for multiple direct memory access transactions and transfer control circuitry responsive to data in the plurality of registers. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the parameters of the plurality of registers. At least two consecutive data transactions are executed with respect to non-contiguous system locations.

Abstract: A device for retaining and supporting pipes having a central curved section between two linear ends and being open to receive one or more pipes therein and serving to protect the pipe from being kinked or bent during construction and post-construction activities. The sides or arms of the device may be extended and bendable such that a pipe may be inserted between the arms and therefore held in place by a spring force. The device may be attached to wall studs or other structures through the use of plumbing straps, which can be weaved through slots in the device to securely hold the pipe(s) in place.

Abstract: A method of replacing a boiling water reactor core shroud includes the steps of removing at least a portion of the existing core shroud from supporting structure in the reactor vessel, lowering a replacement shroud into the reactor vessel, positioning the replacement shroud on the supporting structure such that a bottom portion of the replacement shroud mates cooperatively with the supporting structure to limit lateral movement of the replacement shroud relative to the reactor vessel, and holding the replacement shroud assembly in place by applying axially compressive forces to the shroud in the direction of the supporting structure. If the existing core shroud is secured by welds, a parting cut is made to remove the shroud and the replacement shroud is held in place by securing a plurality of tie rods between sites on the replacement shroud and the supporting structure at a respective plurality of angularly spaced locations about the shroud periphery.

Abstract: A method of replacing a boiling water reactor core shroud includes the steps of removing at least a portion of the existing core shroud from supporting structure in the reactor vessel, lowering a replacement shroud into the reactor vessel, positioning the replacement shroud on the supporting structure such that a bottom portion of the replacement shroud mates cooperatively with the supporting structure to limit lateral movement of the replacement shroud relative to the reactor vessel, and holding the replacement shroud assembly in place by applying axially compressive forces to the shroud in the direction of the supporting structure. If the existing core shroud is secured by welds, a parting cut is made to remove the shroud and the replacement shroud is held in place by securing a plurality of tie rods between sites on the replacement shroud and the supporting structure at a respective plurality of angularly spaced locations about the shroud periphery.