Patents by Inventor William R. Stephenson
William R. Stephenson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220157624Abstract: Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.Type: ApplicationFiled: January 28, 2022Publication date: May 19, 2022Inventors: David R. Hembree, William R. Stephenson
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Patent number: 11239095Abstract: Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.Type: GrantFiled: September 23, 2019Date of Patent: February 1, 2022Assignee: Micron Technology, Inc.Inventors: David R. Hembree, William R. Stephenson
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Publication number: 20200020547Abstract: Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.Type: ApplicationFiled: September 23, 2019Publication date: January 16, 2020Inventors: David R. Hembree, William R. Stephenson
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Patent number: 10424495Abstract: Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.Type: GrantFiled: June 7, 2018Date of Patent: September 24, 2019Assignee: Micron Technology, Inc.Inventors: David R. Hembree, William R. Stephenson
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Publication number: 20180294169Abstract: Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.Type: ApplicationFiled: June 7, 2018Publication date: October 11, 2018Inventors: David R. Hembree, William R. Stephenson
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Patent number: 10083937Abstract: Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. Another group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the first semiconductor die. A further group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the second semiconductor die. Methods of forming semiconductor device packages include aligning first and second semiconductor dice with active surfaces facing each other, the first and second semiconductor dice each including bond pads along a centerline thereof and additional bond pads laterally offset from the centerline thereof.Type: GrantFiled: November 17, 2016Date of Patent: September 25, 2018Assignee: Micron Technology, Inc.Inventors: Anthony D. Veches, William R. Stephenson, Walter L. Moden
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Patent number: 10008395Abstract: Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.Type: GrantFiled: October 19, 2016Date of Patent: June 26, 2018Assignee: Micron Technology, Inc.Inventors: David R. Hembree, William R. Stephenson
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Publication number: 20180108592Abstract: Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.Type: ApplicationFiled: October 19, 2016Publication date: April 19, 2018Inventors: David R. Hembree, William R. Stephenson
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Publication number: 20170069603Abstract: Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. Another group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the first semiconductor die. A further group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the second semiconductor die. Methods of forming semiconductor device packages include aligning first and second semiconductor dice with active surfaces facing each other, the first and second semiconductor dice each including bond pads along a centerline thereof and additional bond pads laterally offset from the centerline thereof.Type: ApplicationFiled: November 17, 2016Publication date: March 9, 2017Applicant: Micron Technology, Inc.Inventors: Anthony D. Veches, William R. Stephenson, Walter L. Moden
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Patent number: 9502369Abstract: Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. Another group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the first semiconductor die. A further group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the second semiconductor die. Methods of forming semiconductor device packages include aligning first and second semiconductor dice with active surfaces facing each other, the first and second semiconductor dice each including bond pads along a centerline thereof and additional bond pads laterally offset from the centerline thereof.Type: GrantFiled: February 4, 2015Date of Patent: November 22, 2016Assignee: Micron Technology, Inc.Inventors: Anthony D. Veches, William R. Stephenson, Walter L. Moden
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Publication number: 20160225734Abstract: Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. Another group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the first semiconductor die. A further group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the second semiconductor die. Methods of forming semiconductor device packages include aligning first and second semiconductor dice with active surfaces facing each other, the first and second semiconductor dice each including bond pads along a centerline thereof and additional bond pads laterally offset from the centerline thereof.Type: ApplicationFiled: February 4, 2015Publication date: August 4, 2016Inventors: Anthony D. Veches, William R. Stephenson, Walter L. Moden
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Patent number: 6916683Abstract: A method and apparatus for encapsulating a BGA package. Specifically, a BGA package is encapsulated after the balls are attached to the package. The backside of the package having the balls disposed thereon may be completely covered by the encapsulant. The encapsulant is disposed in direct contact about a portion of the balls. A liner is provided to facilitate the formation of an unencapsulated portion of each ball. The unencapsulated portion may be used to couple the package to a system.Type: GrantFiled: August 29, 2002Date of Patent: July 12, 2005Assignee: Micron Technology, Inc.Inventors: William R. Stephenson, Bret K. Street, Todd O. Bolken
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Patent number: 6503781Abstract: A method and apparatus for encapsulating a BGA package. Specifically, the molded packaging material is configured to provide cups on the backside of the package, opposite the semiconductor device. The cups expose pads on the substrate and are configured to receive solder balls.Type: GrantFiled: August 6, 2001Date of Patent: January 7, 2003Assignee: Micron Technology, Inc.Inventors: William R. Stephenson, Bret K. Street, Todd O. Bolken
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Publication number: 20020195708Abstract: A method and apparatus for encapsulating a BGA package. Specifically, a BGA package is encapsulated after the balls are attached to the package. The backside of the package having the balls disposed thereon may be completely covered by the encapsulant. The encapsulant is disposed in direct contact about a portion of the balls. A liner is provided to facilitate the formation of an unencapsulated portion of each ball. The unencapsulated portion may be used to couple the package to a system.Type: ApplicationFiled: August 29, 2002Publication date: December 26, 2002Inventors: William R. Stephenson, Bret K. Street, Todd O. Bolken
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Publication number: 20020121695Abstract: A method and apparatus for encapsulating a BGA package. Specifically, the molded packaging material is configured to provide cups on the backside of the package, opposite the semiconductor device. The cups expose pads on the substrate and are configured to receive solder balls.Type: ApplicationFiled: April 11, 2002Publication date: September 5, 2002Inventors: William R. Stephenson, Bret K. Street, Todd O. Bolken
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Patent number: 6400574Abstract: A method and apparatus for encapsulating a BGA package. Specifically, the molded packaging material is configured to provide cups on the backside of the package, opposite the semiconductor device. The cups expose pads on the substrate and are configured to receive solder balls.Type: GrantFiled: May 11, 2000Date of Patent: June 4, 2002Assignee: Micron Technology, Inc.Inventors: William R. Stephenson, Bret K. Street, Todd O. Bolken
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Publication number: 20010046724Abstract: A method and apparatus for encapsulating a BGA package. Specifically, the molded packaging material is configured to provide cups on the backside of the package, opposite the semiconductor device. The cups expose pads on the substrate and are configured to receive solder balls.Type: ApplicationFiled: August 6, 2001Publication date: November 29, 2001Inventors: William R. Stephenson, Bret K. Street, Todd O. Bolken
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Patent number: 4909233Abstract: An adjustable threaded nock set (10) having a pair of serving nuts (11) and (12) having longitudinal bores therethrough. Each bore is threaded to engage monofilament serving (5) of bow string (4). Nuts (11) and (12) are installed onto serving (5) and tightened together at the proper location in a lock nut arrangement.Type: GrantFiled: February 3, 1989Date of Patent: March 20, 1990Inventor: William R. Stephenson
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Patent number: 4776958Abstract: A diatomaceous earth caking filter element includes a first elongated tubular manifold having a slot therein and a suction coupling formed thereon for drawing a liquid from said first manifold. A second elongated tubular manifold has a slot therein and a plurality of hollow pipes connected between the first and second manifolds with one end of each pipe extending into the first manifold through the slot therein and the other end of each pipe extending into the second manifold through the slot therein. Each pipe is held by the slot edges of each manifold extending into an annular groove on each end of each pipe. A filter cake screen covers both sides of the plurality of hollow pipes for catching a filtering medium, such as diatomaceous earth, thereon for filtering liquid passing therethrough, so the liquid can be drawn through the filter medium and filter screen into the first and second manifolds and out the suction coupling.Type: GrantFiled: March 23, 1987Date of Patent: October 11, 1988Inventor: William R. Stephenson