Abstract: A method for processing a wafer with a wafer bevel that surrounds a central region is provided. The wafer is placed in a bevel plasma processing chamber. A protective layer is deposited on the wafer bevel without depositing the protective layer over the central region. The wafer is removed from the bevel plasma processing chamber. The wafer is further processed.

Abstract: A method for preventing formation of metal silicide material on a wafer bevel is provided, where the wafer bevel surrounds a central region of the wafer. The wafer is placed in bevel plasma processing chamber. A protective layer is deposited on the wafer bevel. The wafer is removed from the bevel plasma processing chamber. A metal layer is deposited over at least part of the central region of the wafer, wherein part of the metal layer is deposited over the protective layer. Semiconductor devices are formed while preventing metal silicide formation on the wafer bevel.

Abstract: A method for processing a wafer with a wafer bevel that surrounds a central region is provided. The wafer is placed in a bevel plasma processing chamber. A protective layer is deposited on the wafer bevel without depositing the protective layer over the central region. The wafer is removed from the bevel plasma processing chamber. The wafer is further processed.

Abstract: A method for preventing formation of metal silicide material on a wafer bevel is provided, where the wafer bevel surrounds a central region of the wafer. The wafer is placed in bevel plasma processing chamber. A protective layer is deposited on the wafer bevel. The wafer is removed from the bevel plasma processing chamber. A metal layer is deposited over at least part of the central region of the wafer, wherein part of the metal layer is deposited over the protective layer. Semiconductor devices are formed while preventing metal silicide formation on the wafer bevel.

Abstract: A method is provided for fabricating a semiconductor device having a gate electrode overlying a gate insulator. The method, in accordance with one embodiment, comprises depositing a layer of spin on glass overlying the gate electrode, the layer of spin on glass comprising a substantially UV opaque material. The layer of spin on glass is heated to a temperature less than about 450° C., and all subsequent process steps in the fabrication of the device are limited to temperatures less than about 450° C.

Abstract: A method of fabricating integrated circuits utilizing dual damascene processing when a soft insulative material, such as a polymer, is used. Vertical and horizontal edges of via and conductive line openings are protected from degradation during a second etching step by, prior to the second etching, depositing a hard mask material on each insulative material layer to protect the horizontal edges and depositing a spacer material to protect the vertical edges.