Abstract: A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates the memory functional clock from the memory test clock into two clock paths. The test clocking scheme provides for the ability to separately shut off either the memory functional clock source or the memory test clock source, provides that less power is required during production testing, and provides that simulation time is reduced during design verification because the functional logic is not clocked.

Abstract: Devices and methods of entraining a substance within an airflow are disclosed. Condensation aerosol delivery devices and methods of consistently producing multiple doses of a substance, such as a drug, having high purity, high yield, characterized by a particle size distribution appropriate for pulmonary delivery, and which can be administered to a user in a single dose are also disclosed.

Abstract: Devices comprising a housing defining an airway, at least one support configured to couple to the airway comprising at least one area selected from a first area and a second area, wherein a first compound is disposed on the first area, and a second compound is disposed on the second area, and wherein the second compound can counteract the pharmacological effects of the first compound; and a mechanism configured to release the first compound into the airway, wherein the device comprises at least one first area and at least one second area are disclosed. Methods of producing an aerosol of a first compound comprising providing at least one first area on which is disposed a first compound, and at least one second area on which is disposed a second compound, providing an airflow over at least a portion of the at least one first area, and releasing the first compound from at least a portion of at least one first area into the airflow, wherein the first compound forms an aerosol in the airflow, are also disclosed.

Abstract: A method of testing a core module includes steps of: (a) providing a core module of an integrated circuit design; (b) connecting an end user input and a core module test input to separate I/O pins of the core module to isolate logic associated with an end user signal from that associated with a core module test signal; and (c) multiplexing the end user signal and the core module test signal in the core module in response to a core module test mode signal.

Abstract: In a laying head for forming a longitudinally moving hot rolled product into a helix, a tubular quill has a central axis of rotation and a through passageway extending along the central axis from a first end to an opposite second end of the quill. The interior quill surface has a cylindrical section leading from the first end of the passageway to a radially outwardly flared section which in turn leads to the second end of the passageway. A laying pipe is received in the through passageway. The laying pipe has an entry end aligned with the central axis at the first end of the passageway, a curved intermediate portion surrounded by the flared section of the interior quill surface, and an end portion projecting axially from the second end of the passageway to a delivery end spaced radially from the central axis.

Abstract: A method and system of testing data retention of memory is provided. An embodiment of the method of testing data retention of memory comprises: writing first data to a first memory sub-group during a first time period; writing second data to a second memory sub-group during a second time period subsequent to said first time period; pausing for a predetermined time interval during a third time period subsequent to said second time period; reading a first one of said first and second data during a fourth time period subsequent to said third time period; reading a second one of said first and second data during a fifth time period subsequent to said fourth time period; and comparing said first and second ones of read data to expected results to determine data retention capabilities of said first and second memory sub-groups.