Abstract: A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component to the apparatus for storing information utilizing the clock of the first component, a second component operated in response to the timing of a second clock, apparatus for utilizing the clock of the second component to transfer information from the apparatus for storing information in a condition in which it is synchronized for use by the second component whereby the information may be immediately utilized by the second component without the need for storage by the second component.

Abstract: A circuit for maintaining the order of transmission of information in a computer interconnect including control circuitry for sending a signal from a source of data to a destination for data indicating that data is ready for transfer, the control circuitry comprising a plurality of buffers for storing information relating to the data, the information including information regarding the order in which the information was received by the control circuitry, means for incrementing the information regarding the order in which the information was received by the control circuitry, and apparatus for sending the information relating to the data to the destination for data in the order of receipt by the control circuitry.

Abstract: Apparatus for allowing a component of a computer system to which data is to be written to control the order of transfer of that data including circuitry for providing a numbered signal signifying that a particular component has a set of data which is to be transferred to the destination component, circuitry associated with the destination component for choosing among all of the numbered signals to select from all sets of data a next set of data in a particular numerical order, and circuitry associated with the destination component for selecting other than the next set of data in the particular numerical order.

Abstract: A computer interconnect including a plurality of nodes, each node capable of joining to a component of a computer, each node including apparatus for transferring signals between the component and the node, apparatus for storing packets of data, apparatus for signalling each other node that a packet of data exists for transfer to a component associated with that node, apparatus for sensing signals from another node indicating that a packet of data exists for transfer to a component associated with that node, and apparatus for transferring packets of data stored at one node to the apparatus for transferring signals between the component and the node of another node.

Abstract: To optimize system bus utilization in a computer system, a bus coordinator is included in the computer system to coordinate the transfer of information signals on the bus. Each time a source node wishes to transfer information to a destination node, the source node sends a request to the coordinator along with the identification of the destination node. Upon receiving this request, the coordinator determines whether the destination node has capacity to receive information signals. If the destination node has capacity, then the coordinator grants control of the system bus to the source node to allow the source node to send information signals to the destination node via the system bus. Otherwise, the source node is denied control of the system bus until the destination node has capacity to receive information signals.

Abstract: A bus system uses separate clocks for arbitration and data transfer. The arbitration clock signal is used for synchronizing bus request and grant events, and the data clock signal is used for synchronizing data transmission and reception. In particular, the data clock signal, which is generated by a bus master node without any temporal relationship to the arbitration clock signal, is transmitted by the bus master node through the bus to a slave node, where the received data signal is synchronized with the data clock signal transmitted therewith.

Abstract: In a bus system including a bus, a plurality of nodes including a primary node, and a bus access coordinator, bus utilization efficiency is improved by operating the coordinator at the same clock frequency as the primary node. The primary node is the node in the bus system which accesses the bus most frequently. By running the coordinator synchronous with the primary node, the need for synchronization events between the two components is eliminated. Since the primary node accesses the bus most frequently, eliminating synchronization events with the primary node eliminates most of the synchronization events in the bus system. Thus, synchronization events are minimized which, in turn, improves bus utilization efficiency.

Abstract: A semaphore method establishes exclusive access transactions between source and destination nodes in a multiple bus computer system, independent of the bus locking architectures of the component buses. An atomic transaction is selected for each bus protocol to mediate exclusive access transactions involving the corresponding bus, and bridges coupling different pairs of buses monitor these buses for the selected atomic transactions. A source node on one bus (the source bus) initiates an exclusive access transaction to a destination node by launching the selected atomic transaction appropriate for the source bus to the destination node. When the path between the source and the destination nodes requires transit of more than one bus, each bridge that couples a pair of buses in the path detects an incoming atomic transaction on one of these buses and launches an outgoing atomic transactions appropriate for the other bus to the destination node.

Abstract: A system for pipelining bus requests includes a bus, at least one node coupled to the bus, and a bus coordinator coupled to the node. The node uses a single bus request signal to both request control of the bus from the bus coordinator, and to retain control of the bus. In response to an asserted bus request signal from the node, the coordinator sends an asserted bus grant signal to the node to grant the node control of the bus. This bus grant signal tracks the bus request signal so that as long as the bus request signal remains asserted, the bus grant signal also is asserted. To allow for pipelining, the bus coordinator maintains the bus grant signal in an asserted state for at least one clock cycle after the bus request is deasserted. By holding the bus grant signal in the asserted state for one extra cycle, the coordinator gives the node time to deassert and then to reassert the bus request signal before the bus grant signal changes state.

Abstract: Signal transactions are conducted between nodes coupled to a bus, without causing bus deadlock during split transactions. Deadlock avoidance is achieved by rendering a node effectively unavailable at such times to serve as a bus slave for a new bus master. When the "locking" node serves as a transaction source, deadlock is avoided by deasserting, during a split transaction, a buffer-available signal, which is used normally to indicate receiver buffer availability. Additionally, when the "locking" node serves as a transaction destination, deadlock is avoided by deasserting a bus-ownership request signal, which is used normally for requesting bus ownership. After completion of the split transactions, such signals may be unmasked.

Abstract: A circuit which includes apparatus for determining for at each node of a multi-node interconnect the highest priority data present for transfer to that node, apparatus for storing information indicating the last node from which a transfer of data occurred at each priority level, apparatus for selecting for each priority level of data available at the node the last node from which a transfer of data occurred at each priority level, apparatus for weighting data at each priority level depending on the data last chosen at that level of priority, and means for selecting from all of the data available at each node the data having both the highest priority and having been chosen least recently at that priority levels of data at that node.

Abstract: A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component to the apparatus for storing information utilizing the clock of the first component, a second component operated in response to the timing of a second clock, apparatus for utilizing the clock of the second component to transfer information from the apparatus for storing information in a condition in which it is synchronized for use by the second component whereby the information may be immediately utilized by the second component without the need for storage by the second component.