Patents by Inventor William T. Lee
William T. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240127206Abstract: An ATM is configured to interact with a mobile device and provide user access to one or more of the banking services available at the ATM using the mobile device. Banking-related information may be viewed and/or input at the ATM using the mobile device. The ATM may have multiple vertical levels of deposit slots, withdrawal trays and/or receipt dispensers. A level at the ATM at which the user interacts with the ATM for deposits, withdrawals, or receipts may be selected. The level may be specified by the user of the mobile device, at the ATM or using the mobile device, or may be determined by the ATM.Type: ApplicationFiled: October 13, 2022Publication date: April 18, 2024Inventors: Arjun Thimmareddy, Bryan T. King, Alexander S. Lee, Vaishnavi Varma, Tony Aidoo, Paula M. Booze, Ramesh B. Chandanala, William R. Conrad, Juliet Abdul-Aziz, Gerard P. Gay
-
Patent number: 11948136Abstract: An ATM is configured to interact with a mobile device and provide user access to one or more of the banking services available at the ATM using the mobile device. Banking-related information may be viewed and/or input at the ATM using the mobile device. The ATM may have multiple vertical levels of deposit slots, withdrawal trays and/or receipt dispensers. A level at the ATM at which the user interacts with the ATM for deposits, withdrawals, or receipts may be selected. The level may be specified by the user of the mobile device, at the ATM or using the mobile device, or may be determined by the ATM.Type: GrantFiled: October 13, 2022Date of Patent: April 2, 2024Assignee: Bank of America CorporationInventors: Arjun Thimmareddy, Bryan T. King, Alexander S. Lee, Vaishnavi Varma, Tony Aidoo, Paula M. Booze, Ramesh B. Chandanala, William R. Conrad, Juliet Abdul-Aziz, Gerard P. Gay
-
Publication number: 20240104533Abstract: A screen-less automated teller machine (ATM) may be configured to interact with a mobile device. The ATM may automatically detect the presence of the mobile device in a vicinity of the ATM and initiate contact with the mobile device, or a mobile device may initiate contact with the ATM. After verifying user permission to access the ATM, the mobile device may be enabled to provide user access to one or more of the banking services available at the ATM using the mobile device. As the ATM is screen-less, banking-related information may be viewed and/or input at the ATM using the mobile device. An application on the mobile device may be used to access and interact with the ATM using the mobile device.Type: ApplicationFiled: September 22, 2022Publication date: March 28, 2024Inventors: Arjun Thimmareddy, Bryan T. King, Alexander S. Lee, Vaishnavi Varma, Tony Aidoo, Paula M. Booze, Ramesh B. Chandanala, William R. Conrad, Juliet Abdul-Aziz, Gerard P. Gay
-
Publication number: 20240095698Abstract: Methods for banking at an automated teller machine (ATM) using a mobile device. The ATM may automatically detect the presence of the mobile device in a vicinity of the ATM and initiate contact with the mobile device, or a mobile device may initiate contact with the ATM. After verifying user permission to access the ATM, the mobile device may be enabled to provide user access to one or more of the banking services available at the ATM using the mobile device and to view banking-related information on the mobile device. A mobile application on the mobile device may be used to access the ATM using the mobile device. While a mobile device is accessing the ATM, a screen on the ATM may become inactive for banking services and the option to select banking services directly at the ATM may be disabled.Type: ApplicationFiled: September 15, 2022Publication date: March 21, 2024Inventors: Arjun Thimmareddy, Bryan T. King, Alexander S. Lee, Vaishnavi Varma, Tony Aidoo, Paula M. Booze, Ramesh B. Chandanala, William R. Conrad, Juliet Abdul-Aziz, Gerard P. Gay
-
Patent number: 10262943Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: GrantFiled: January 23, 2018Date of Patent: April 16, 2019Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
-
Patent number: 10128116Abstract: Efficient integrated sequential deposition of alternating layers of dielectric and conductor, for example oxide/metal or metal nitride, e.g., SiO2/TiN, in a single tool, and even in a single process chamber enhances throughput without compromising quality when directly depositing a OMOM stack with many layers. Conductor and dielectric film deposition of a stack of at least 20 conductor/dielectric film pairs in the same processing tool or chamber, without breaking vacuum between the film depositions, such that there is no substantial cross-contamination between the conductor and dielectric film depositions, can be achieved.Type: GrantFiled: May 11, 2017Date of Patent: November 13, 2018Assignee: LAM RESEARCH CORPORATIONInventors: William T. Lee, Bart J. van Schravendijk, David Charles Smith, Michal Danek, Patrick A. Van Cleemput, Ramesh Chandrasekharan
-
Publication number: 20180151503Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: ApplicationFiled: January 23, 2018Publication date: May 31, 2018Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
-
Publication number: 20180108529Abstract: Efficient integrated sequential deposition of alternating layers of dielectric and conductor, for example oxide/metal or metal nitride, e.g., SiO2/TiN, in a single tool, and even in a single process chamber enhances throughput without compromising quality when directly depositing a OMOM stack with many layers. Conductor and dielectric film deposition of a stack of at least 20 conductor/dielectric film pairs in the same processing tool or chamber, without breaking vacuum between the film depositions, such that there is no substantial cross-contamination between the conductor and dielectric film depositions, can be achieved.Type: ApplicationFiled: May 11, 2017Publication date: April 19, 2018Inventors: William T. Lee, Bart J. van Schravendijk, David Charles Smith, Michal Danek, Patrick A. Van Cleemput, Ramesh Chandrasekharan
-
Patent number: 9875968Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: GrantFiled: February 24, 2017Date of Patent: January 23, 2018Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
-
Publication number: 20170162512Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: ApplicationFiled: February 24, 2017Publication date: June 8, 2017Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
-
Patent number: 9583386Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: GrantFiled: October 2, 2015Date of Patent: February 28, 2017Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
-
Patent number: 9418889Abstract: A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric.Type: GrantFiled: June 17, 2015Date of Patent: August 16, 2016Assignee: Lam Research CorporationInventors: Thomas Weller Mountsier, Hui-Jung Wu, Bhadri N. Varadarajan, Nagraj Shankar, William T. Lee
-
Publication number: 20160118296Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: ApplicationFiled: October 2, 2015Publication date: April 28, 2016Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
-
Publication number: 20150380302Abstract: A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric.Type: ApplicationFiled: June 17, 2015Publication date: December 31, 2015Inventors: Thomas Weller Mountsier, Hui-Jung Wu, Bhadri N. Varadarajan, Nagraj Shankar, William T. Lee
-
Patent number: 9184060Abstract: The embodiments herein relate to methods, apparatus, and systems for forming recessed features at high aspect ratios. Often, such features are formed in the context of fabricating a vertical NAND (VNAND) memory device. Various disclosed embodiments relate to process flows that involve depositing and shaping sacrificial posts on a metal seed layer that covers an underlying stack of materials, electroplating or electroless plating metal hard mask material around the sacrificial posts, removing the sacrificial posts, and etching the underlying stack of materials to form a high aspect ratio recessed feature.Type: GrantFiled: November 14, 2014Date of Patent: November 10, 2015Assignee: Lam Research CorporationInventor: William T. Lee
-
Patent number: 9006893Abstract: An electronic device which in one embodiment comprises a metallization stack is provided. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited electrolessly. Additionally, the barrier metal contacts the wetting layer, where the wetting layer is wettable by solder.Type: GrantFiled: August 22, 2013Date of Patent: April 14, 2015Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Fritz Redeker
-
Patent number: 8828863Abstract: A method for providing metal filled features in a layer is provided. A nonconformal metal seed layer is deposited on tops, sidewalls, and bottoms of the features, wherein more seed layer is deposited on tops and bottoms of features than sidewalls. The metal seed layer are etched back on tops, sidewalls, and bottoms of the features, wherein some metal seed layer remains on tops and bottoms of the features. Deposition on the seed layer on tops of the features is suppressed. An electroless “bottom up” deposition of metal is provided to fill the features.Type: GrantFiled: June 25, 2013Date of Patent: September 9, 2014Assignee: Lam Research CorporationInventors: William T. Lee, Xiaomin Bin
-
Patent number: 8673779Abstract: A method of filling of vias and trenches in a dual damascene structure with a filling comprising copper or copper alloy is provided. An electroless deposition filling of the vias with a via filling comprising copper or copper alloy is provided. A trench barrier layer is formed over the via filling with a trench barrier layer comprising Mn or Al. The trench barrier layer is annealed at a temperature that causes a component of the trench barrier layer to pass into the via filling. The trenches are filled with a trench filling comprising copper or copper alloy.Type: GrantFiled: February 27, 2013Date of Patent: March 18, 2014Assignee: Lam Research CorporationInventors: Hyungsuk A. Yoon, William T. Lee
-
Publication number: 20140054776Abstract: A method of making an electronic device which in one embodiment comprises providing a substrate, electrolessly depositing a barrier metal at least on portions of the substrate, and using wet chemistry such as electroless deposition to deposit a substantially gold-free wetting layer having solder wettability onto the barrier metal. An electronic device which in one embodiment comprises a metallization stack. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited on the barrier metal, and the wetting layer is wettable by solder.Type: ApplicationFiled: August 22, 2013Publication date: February 27, 2014Applicant: Lam Research CorporationInventors: Artur KOLICS, William T. LEE, Fritz REDEKER
-
Patent number: 8518815Abstract: A method of making an electronic device which in one embodiment comprises providing a substrate, electrolessly depositing a barrier metal at least on portions of the substrate, and using wet chemistry such as electroless deposition to deposit a substantially gold-free wetting layer having solder wettability onto the barrier metal. An electronic device which in one embodiment comprises a metallization stack. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited on the barrier metal, and the wetting layer is wettable by solder.Type: GrantFiled: July 7, 2010Date of Patent: August 27, 2013Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Fritz Redeker