Patents by Inventor William T. Rericha
William T. Rericha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140147542Abstract: A method of forming a template for use in imprint lithography. The method comprises providing an ultraviolet (“UV”) wavelength radiation transparent layer and forming a pattern in the UV transparent layer by photolithography. The pattern may be formed by anisotropically etching the UV transparent layer and may have feature dimensions of less than approximately 100 nm, such as dimensions of less than approximately 45 nm. An additional embodiment of the method comprises providing a UV opaque layer comprising a first pattern therein, forming a first UV transparent layer in contact with the first pattern of the UV opaque layer, forming a second UV transparent layer in contact with the first UV transparent layer, and removing the UV opaque layer to form the template. An intermediate template structure for use in imprint lithography is also disclosed. In other embodiments, a template that is opaque to UV wavelength radiation and a method of forming the same are disclosed.Type: ApplicationFiled: January 30, 2014Publication date: May 29, 2014Applicant: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, William T. Rericha
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Patent number: 8674512Abstract: Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction.Type: GrantFiled: December 21, 2012Date of Patent: March 18, 2014Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Randal W. Chance, William T. Rericha
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Patent number: 8657597Abstract: A method of forming a template for use in imprint lithography. The method comprises providing an ultraviolet (“UV”) wavelength radiation transparent layer and forming a pattern in the UV transparent layer by photolithography. The pattern may be formed by anisotropically etching the UV transparent layer and may have feature dimensions of less than approximately 100 nm, such as dimensions of less than approximately 45 nm. An additional embodiment of the method comprises providing a UV opaque layer comprising a first pattern therein, forming a first UV transparent layer in contact with the first pattern of the UV opaque layer, forming a second UV transparent layer in contact with the first UV transparent layer, and removing the UV opaque layer to form the template. An intermediate template structure for use in imprint lithography is also disclosed. In other embodiments, a template that is opaque to UV wavelength radiation and a method of forming the same are disclosed.Type: GrantFiled: July 20, 2010Date of Patent: February 25, 2014Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, William T. Rericha
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Patent number: 8598632Abstract: An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.Type: GrantFiled: June 22, 2012Date of Patent: December 3, 2013Assignee: Round Rock Research LLCInventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
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Patent number: 8338085Abstract: Alignment tolerances between narrow mask lines and wider mask lines in an integrated circuit are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. The narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, a shadowing effect causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction.Type: GrantFiled: December 11, 2009Date of Patent: December 25, 2012Assignee: Micron Technology, Inc.Inventors: Gurtej S Sandhu, Randal W Chance, William T Rericha
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Publication number: 20120256309Abstract: An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.Type: ApplicationFiled: June 22, 2012Publication date: October 11, 2012Inventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi (Jenny) Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
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Patent number: 8216949Abstract: A method lor integrated circuit fabrication is disclosed. A spacer pattern is provided including a plurality ot spacers in an array region of a partially-fabricated integrated circuit. Each spacer is at least partly defined by opposing open volumes extending along lengths of the spacers. A pattern is subsequently defined in a periphery region of the partially-fabricated integrated circuit. A consolidated pattern is formed by concurrently transferring the spacer pattern and the pattern in the periphery region into an underlying masking layer. The consolidated pattern is transferred to an underlying substrate.Type: GrantFiled: February 17, 2010Date of Patent: July 10, 2012Assignee: Round Rock Research, LLCInventors: Mirzafer K Abatchev, Gurtej Sandhu, Luan Tran, William T Rericha, D. Mark Durcan
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Patent number: 8207576Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.Type: GrantFiled: January 31, 2007Date of Patent: June 26, 2012Assignee: Round Rock Research, LLCInventors: Luan Tran, William T Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K Abatchev, Gurtej S Sandhu, D. Mark Durcan
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Patent number: 8119535Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.Type: GrantFiled: December 11, 2009Date of Patent: February 21, 2012Assignee: Round Rock Research, LLCInventors: Luan Tran, William T Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K Abatchev, Gurtej S Sandhu, D. Mark Durcan
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Patent number: 8048812Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.Type: GrantFiled: April 28, 2010Date of Patent: November 1, 2011Assignee: Round Rock Research, LLCInventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
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Publication number: 20100285167Abstract: A method of forming a template for use in imprint lithography. The method comprises providing an ultraviolet (“UV”) wavelength radiation transparent layer and forming a pattern in the UV transparent layer by photolithography. The pattern may be formed by anisotropically etching the UV transparent layer and may have feature dimensions of less than approximately 100 nm, such as dimensions of less than approximately 45 nm. An additional embodiment of the method comprises providing a UV opaque layer comprising a first pattern therein, forming a first UV transparent layer in contact with the first contact pattern of the UV opaque layer, forming a second UV transparent layer in contact with the first UV transparent layer, and removing the UV opaque layer to form the template. An intermediate template structure for use in imprint lithography is also disclosed. In other embodiments, a template that is opaque to UV wavelength radiation and a method of forming the same are disclosed.Type: ApplicationFiled: July 20, 2010Publication date: November 11, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Gurtej S. Sandhu, William T. Rericha
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Publication number: 20100210111Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.Type: ApplicationFiled: April 28, 2010Publication date: August 19, 2010Applicant: ROUND ROCK RESEARCH, LLCInventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi (Jenny) Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
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Publication number: 20100203727Abstract: Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern.Type: ApplicationFiled: February 17, 2010Publication date: August 12, 2010Applicant: Micron Technology, Inc.Inventors: Mirzafer K. Abatchev, Gurtej Sandhu, Luan Tran, William T. Rericha, D. Mark Durcan
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Patent number: 7771917Abstract: A method of forming a template for use in imprint lithography. The method comprises providing an ultraviolet (“UV”) wavelength radiation transparent layer and forming a pattern in the UV transparent layer by photolithography. The pattern may be formed by anisotropically etching the UV transparent layer and may have feature dimensions of less than approximately 100 nm, such as dimensions of less than approximately 45 nm. An additional embodiment of the method comprises providing a UV opaque layer comprising a first pattern therein, forming a first UV transparent layer in contact with the first contact-pattern of the UV opaque layer, forming a second UV transparent layer in contact with the first UV transparent layer, and removing the UV opaque layer to form the template. An intermediate template structure for use in imprint lithography is also disclosed. In other embodiments, a template that is opaque to UV wavelength radiation and a method of forming the same are disclosed.Type: GrantFiled: June 17, 2005Date of Patent: August 10, 2010Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, William T. Rericha
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Patent number: 7718540Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.Type: GrantFiled: February 1, 2007Date of Patent: May 18, 2010Assignee: Round Rock Research, LLCInventors: Luan Tran, William T Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K Abatchev, Gurtej S Sandhu, D. Mark Durcan
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Publication number: 20100092891Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.Type: ApplicationFiled: December 11, 2009Publication date: April 15, 2010Applicant: Micron Technology, Inc.Inventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
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Publication number: 20100092890Abstract: Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction.Type: ApplicationFiled: December 11, 2009Publication date: April 15, 2010Applicant: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Randal W. Chance, William T. Rericha
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Patent number: 7687408Abstract: Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern.Type: GrantFiled: March 8, 2007Date of Patent: March 30, 2010Assignee: Micron Technology, Inc.Inventors: Mirzafer K. Abatchev, Gurtej Sandhu, Luan Tran, William T. Rericha, D. Mark Durcan
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Patent number: 7655387Abstract: Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction.Type: GrantFiled: September 2, 2004Date of Patent: February 2, 2010Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Randal W. Chance, William T. Rericha
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Patent number: 7651951Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.Type: GrantFiled: March 1, 2007Date of Patent: January 26, 2010Assignee: Micron Technology, Inc.Inventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan