Patents by Inventor William Tsai

William Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11980633
    Abstract: Described herein are methods of treating a proliferative disease in a subject by administering a DNA-damaging agent and between about 8 and about 48 hours later administering to the subject a DNA-PK inhibitor. Exemplary DNA-PK inhibitors are represented by Formula (B-I): and by pharmaceutically acceptable salts thereof, wherein R1, Q, Ring A, and Ring B are as defined herein.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: May 14, 2024
    Assignee: Vertex Pharmaceuticals Incorporated
    Inventors: Diane Boucher, Shawn M. Hillier, Wanjung Tsai, Brian Hare, William Markland, David A. Newsome, Marina S. Penney
  • Publication number: 20240084107
    Abstract: A polymer composition comprises a polypropylene polymer and a salt of a branched alkyl phosphonic acid.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Inventors: Darin Dotson, Xiaoyou XU, Hua Sun, Chi-Chun Tsai, Corey Williams
  • Patent number: 9984527
    Abstract: Disclosed are systems, devices and methods for providing solar lighting and power to a customer by using pay-as-you-go (PAYG) technology. The PAYG technology allows a customer to make incremental payments for a solar energy system that includes a lighting unit. The payments can be made through a smartphone. A cable is used to connect an audio jack of the smartphone and a PV power jack of the lighting unit. Analog AC signals including data about activation, payment, usage and status are transmitted over the cable between the service provider and lighting unit, through a smartphone. The power jack of the lighting unit is also used to connect to a solar panel of a charging unit and a battery of the lighting unit.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 29, 2018
    Assignee: Angaza Design, Inc.
    Inventors: Lesley Silverthorn Marincola, Bryan Silverthorn, Victoria Arch, Lee Silverthorn, Joshua Milburn, William Tsai, Eric Thorne
  • Publication number: 20170116813
    Abstract: Disclosed are systems, devices and methods for providing solar lighting and power to a customer by using pay-as-you-go (PAYG) technology. The PAYG technology allows a customer to make incremental payments for a solar energy system that includes a lighting unit. The payments can be made through a smartphone. A cable is used to connect an audio jack of the smartphone and a PV power jack of the lighting unit. Analog AC signals including data about activation, payment, usage and status are transmitted over the cable between the service provider and lighting unit, through a smartphone. The power jack of the lighting unit is also used to connect to a solar panel of a charging unit and a battery of the lighting unit.
    Type: Application
    Filed: September 1, 2016
    Publication date: April 27, 2017
    Applicant: Angaza Design, Inc.
    Inventors: Lesley Silverthorn MARINCOLA, Bryan SILVERTHORN, Victoria ARCH, Lee SILVERTHORN, Joshua MILBURN, William TSAI, Eric THORNE
  • Patent number: 9437070
    Abstract: Disclosed are systems, devices and methods for providing solar lighting and power to a customer by using pay-as-you-go (PAYG) technology. The PAYG technology allows a customer to make incremental payments for a solar energy system that includes a lighting unit. The payments can be made through a smartphone. A cable is used to connect an audio jack of the smartphone and a PV power jack of the lighting unit. Analog AC signals including data about activation, payment, usage and status are transmitted over the cable between the service provider and lighting unit, through a smartphone. The power jack of the lighting unit is also used to connect to a solar panel of a charging unit and a battery of the lighting unit.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 6, 2016
    Assignee: Angaza Design, Inc.
    Inventors: Lesley Silverthorn Marincola, Bryan Silverthorn, Victoria Arch, Lee Silverthorn, Joshua Milburn, William Tsai, Eric Thorne
  • Publication number: 20150287263
    Abstract: Disclosed are systems, devices and methods for providing solar lighting and power to a customer by using pay-as-you-go (PAYG) technology. The PAYG technology allows a customer to make incremental payments for a solar energy system that includes a lighting unit. The payments can be made through a smartphone. A cable is used to connect an audio jack of the smartphone and a PV power jack of the lighting unit. Analog AC signals including data about activation, payment, usage and status are transmitted over the cable between the service provider and lighting unit, through a smartphone. The power jack of the lighting unit is also used to connect to a solar panel of a charging unit and a battery of the lighting unit.
    Type: Application
    Filed: March 18, 2015
    Publication date: October 8, 2015
    Applicant: ANGAZA DESIGN, INC.
    Inventors: Lesley Silverthorn MARINCOLA, Bryan SILVERTHORN, Victoria ARCH, Lee SILVERTHORN, Joshua MILBURN, William TSAI, Eric THORNE
  • Patent number: 8686402
    Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 1, 2014
    Inventors: Niti Goel, William Tsai, Jack Kavalieros
  • Publication number: 20100038713
    Abstract: A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body.
    Type: Application
    Filed: August 13, 2008
    Publication date: February 18, 2010
    Inventors: Prashant Majhi, William Tsai, Jack Kavalieros, Ravi Pillarisetty, Benjamin Chu-Kung
  • Patent number: 7545003
    Abstract: A process for forming defect-free source and drain extensions for a MOSFET built on a germanium based channel region deposits a first silicon germanium layer on a semiconductor substrate, deposits a gate dielectric layer on the silicon germanium layer, and deposits a gate electrode layer on the gate dielectric layer. A dry etch chemistry etches those layers to form a gate electrode, a gate dielectric, and a silicon germanium channel region on the semiconductor substrate. Next, an ion implantation process forms halo implant regions that consume portions of the silicon germanium channel region and the semiconductor substrate. Finally, an in-situ doped epitaxial deposition process grows a pair of silicon germanium layers having LDD regions. The silicon germanium layers are adjacent to the silicon germanium channel region and the halo implant regions do not damage any portion of the silicon germanium layers.
    Type: Grant
    Filed: September 29, 2007
    Date of Patent: June 9, 2009
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, William Tsai, Jack T. Kavalieros
  • Publication number: 20090085129
    Abstract: A process for forming defect-free source and drain extensions for a MOSFET built on a germanium based channel region deposits a first silicon germanium layer on a semiconductor substrate, deposits a gate dielectric layer on the silicon germanium layer, and deposits a gate electrode layer on the gate dielectric layer. A dry etch chemistry etches those layers to form a gate electrode, a gate dielectric, and a silicon germanium channel region on the semiconductor substrate. Next, an ion implantation process forms halo implant regions that consume portions of the silicon germanium channel region and the semiconductor substrate. Finally, an in-situ doped epitaxial deposition process grows a pair of silicon germanium layers having LDD regions. The silicon germanium layers are adjacent to the silicon germanium channel region and the halo implant regions do not damage any portion of the silicon germanium layers.
    Type: Application
    Filed: September 29, 2007
    Publication date: April 2, 2009
    Inventors: Prashant Majhi, William Tsai, Jack Kavalieros